Part Number: DRA829J-Q1
Tool/software:
Hello,
refering to DRA829J-Q1: PORz_OUT driven high before MCU_PORz going high - Processors forum - Processors - TI E2E support forums,
Bill assumed that the pulse on PORz_OUT is occurring before the SOC_PORz_1V8's open-drain supply VDA_MCU_1V8 is enabled at 1.7ms, and that any modulations of prior to enabling of the open-drain reference voltage should be ignored since the SOC_PORz_1V8 signal is not fully activated.
I did a further measurement which shows that the high pulse occurs after VDA_MCU_1V8 is fully powered.
dark blue: PMIC A GPIO11, with pullup to VDA_MCU_1V8
light blue: same signal after a schmitt trigger gate, supplied with VDA_MCU_1V8
purple: PORz_out
green: VDA_MCU_1V8
So for me it´s still not clear where this PORz_out high pulse is coming from, as the only driver is the Jacinto itself.
I also suppose there is no impact on latching of bootmode settings as these are driven again by HW during the second low phase of PORz_out, and should be captured correctly with the second rising edge of PORz_out.
Do you see a necessity to search deeper for the root cause of the pulse which occurs after enabling of the open-drain reference voltage contrary to you assumption before?
Regards, Peter
