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AM623: AM623 Radiated Emissions

John Booth64
Prodigy 140 points
Part Number: AM623

Tool/software:

We have an AM623 design where we battling a radiated emission problem.  The issue has persisted after 2 attempted PCB modifications.  From what we can determine the primary source of the 700 MHz and 900 MHz radiated emission is the GPMC_CLK (7th and 9th harmonic of 100 MHz) coming out of PLL2.  We see a significant, but not complete reduction of an H-field measurement if we disable PLL2.  We also know that the H field persists even when we remove the source termination resistor from the GPMC_CLK line that routes to an adjacent FPGA.  We believe we have adequate decoupling and low enough Power Distribution Impedance on the associated power supplies, but somehow a current loop is apparently being created.  We would like TIs assistance in trying to solve this problem.

  • 0
    TI__Guru**** 191939 points

    Hello John Booth64,

    Thank you for the query.

    I am assigning the query to the expert to support.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru 63105 points

    Hello John,

    As you know, we already discussed this topic on the phone and there have been some follow-up emails describing what has been tried since we last talked.

    One of the emails mentioned the remaining GMPC signal were disabled, and you didn't see any impact. We want to make sure you set bit 21 (TX_DIS) high on all GPMC PADCONFIG registers 15-45 at the same time when performing the test.

    The email also mentioned disabling the GPMC clock output via PADCONFIG32 or HSDIV produced similar insignificant results, but disabling PLL2 had a much more significant impact. This would seem to indicate the emissions could be coming from one of the other peripherals being clocked by PLL2. If so, you may need to try eliminating some of these peripherals. For example, each of the three MMCSD host controllers as well as the GPMC module have the option of being clocked from PLL0 or PLL2. You may want to change the clock source of these peripherals to see how this impacts your emissions.

    You may also want to change the HSDIV clock divider to operate these modules at a frequency that is not as likely to produce a harmonic in the problem frequency range. For example, change MAIN_PLL2_HSDIV7_CLKOUT or MAIN_PLL0_HSDIV3_CLKOUT to generate a 66MHz or 80MHz clock to the GPMC module rather than using the 100MHz option, and change MAIN_PLL2_HSDIV2_CLKOUT or MAIN_PLL0_HSDIV5_CLKOUT to generate a 181.8MHz or 166MHz clock to the MMCSD modules rather than using the 200MHz option. Note: The HSDIVs and the frequency options mentioned above are based on these modules being sourced from PLL2 or PLL0. 

    Please reply to this thread and provide an updated summary of what you have tested and the result of each test.

    Regards,
    Paul