TMDS64EVM: Logic Level Compatibility Issue Between CDCLVC1310RHBR (1.8V IO) and DP83867IRRGZ / DP83869HMRGZT (3.3V IO)

Tool/software:

Hello,

We are using the TMDS64EVM board in our design, where the CDCLVC1310RHBR clock buffer (operating at 1.8V IO) is connected to the DP83867IRRGZ and DP83869HMRGZT Ethernet PHYs, which are powered at 3.3V.Upon reviewing the datasheets and performing logic level compatibility checks, it is failing. This raises concerns about potential signal integrity or logic recognition issues. Is this connection valid as per TI’s design guidelines?

Thanks,

Pradeepraj M