TDA4VEN-Q1: PLL7 (C7x PLL)

sprujb3b Section 6.4.5.2 lists PLL7 (C7x PLL), however, Figure 6-36 does not show PLL7 (C7x PLL). Is this an omission?
>> PLL7 should be in Figure 6-36

sprujb3b Section 6.4.5.3.2 does not include n=7 as a possibility. Is this correct?
>> Section 6.4.5.3.2 should include n = 7; these registers are shown in J722S_Registers_Public_20250115

sprujb3b Figure 6-28 shows the C7xv (2x) block being clocked by GPU PLL. Is this correct?
>> no, the C7x is clocked by the C7x PLL; the GPU PLL plays no part in the C7x clocking scheme

sprujb3b Figure 6-36 shows only MCU_HFOSC0_CLKOUT as a source to all Main Domain PLLs. However, the register descriptions seem to indicate that EXT_REFCLK1 is also possible.
>> hey, I think the TRM is right on this topic!  The MCU_HFOSC0_CLKOUT is the source for the C7x PLL. EXT_REFCLK1 is not a possibility

Please also confim that HFOSC0_CLKOUT and MCU_HFOSC0_CLKOUT are synonyms.
>> confirmed.

sprsp96a Section 6.9.4.3 does not mention VIDEO PLL nor C7x PLL. Is this correct?
>> not sure what is asked.

Kevin

Hello Kevin,

Thank you for the quick response!

Kevin Lavery said:

The MCU_HFOSC0_CLKOUT is the source for the C7x PLL. EXT_REFCLK1 is not a possibility

OK, so MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL7_PROXY (in J722S_Registers_Public_20250115) is indeed only for some kind of test mode?

sprujb3b Table 5-54 Source Index seems to indicate that EXT_REFCLK1 is useable as a source to some of the PLLs. Which ones, please? This is a bit difficult to decypher.

Kevin Lavery said:

sprsp96a Section 6.9.4.3 does not mention VIDEO PLL nor C7x PLL. Is this correct?
>> not sure what is asked.

It seems as if those two PLLs should also have been listed in that section in the datasheet (sprsp96a).