TDA4VM: DSP memory allocation

Hi,

?? ? said:

Why is the stack memory of TDA4VM's C66x all located in DDR

Could you please confirm which kernels you are referring to? For DSPLIB kernels, memory is allocated in L2SRAM. However, in the case of Vision Apps, memory is allocated in DDR since the L1 and L2 SRAM are too small to accommodate the firmware images.

Regards,
Shabary S Sundar

In the case of Vision Apps, is it impossible for our self-implemented algorithms to be locked in L2 memory? 

Hi,

?? ? said:

In the case of Vision Apps, is it impossible for our self-implemented algorithms to be locked in L2 memory? 

You cannot fit the entire algorithm and operations completely within L2 memory. The boot firmware images and related files, which consume significant memory, must be placed in DDR. For improved performance, you can try to copy the input data images from DDR to L2 memory using DMA.

You can also refer the following example:
ti-processor-sdk-rtos-j721e-evm-11_00_00_06\vision_apps\apps\basic_demos\app_c7x_kernel\c7x\app_c7x_target_kernel_img_add

Regards,
Shabary S Sundar

Our algorithm is less than 4KB in size and should theoretically fit in the L2 memory. However, the current situation is that when I attempt to lock it in the L2 memory, the following error occurs, preventing normal startup.

Hi,

?? ? said:

the following error occurs, preventing normal startup

The error can be due to the algorithm accessing L2 memory before the system finished setting up its memory mapping and loading all required firmware, causing an invalid memory access crash.

Could you please confirm the size of your input and where it is stored? It is generally recommended to keep the code in DDR memory. For better efficiency, the data can be moved from DDR to L2 memory.

Also, could you confirm which algorithm or operation you are trying to perform? Additionally, please share any linker script changes you have made to lock it in L2 memory.

Regards,
Shabary S Sundar