AM67A: QSPI boot

Hello Ryuuichi Machida-san,

We are currently working through this with the expert. 

Please ping the thread if you do not get the answers early next week.

We appreciate your patience !

Kind Regards,

Anastas Yordanov

Hi Anastas,

Thank you for your reply.
I' will wait for your feedback.
If possible, could you check status of following other stacked thread as well ?

* AM67A: External reference clock requirement for SERDES function - Processors forum - Processors - TI E2E support forums
* AM67A: Trace requirement for PCIe reference clock - Processors forum - Processors - TI E2E support forums

Best Regards,

Hello Ryuuichi Machida-san,

In the meantime, 

Ryuuichi machida said:

If possible, could you check status of following other stacked thread as well ?

I've checked the status as requested. There is already another TI expert assigned to handle the above two threads.

Thanks

Kind Regards,

Anastas Yordanov

Hello Ryuuichi Machida-san,

The section 12.3.2.4.1 Read Data Capture of the AM67A TRM specifies that the DQS pin is not available at the QSPI memory side. 

For the details of QSPI specific booting, please refer to the section QSPI Boot of the AM67A TRM.

The section QSPI Bootloader Operation of the AM67A TRM specifies that the quad read speed is 50 MHz. From these sections I understand that TAP (No-PHY) SDR mode is supported by the AM67A RBL QSPI Bootloader. 

The description of issue i2249 OSPI: Internal PHY Loopback and Internal Pad Loopback clocking modes with DDR timing inoperable .... of the AM67A Silicon Revision 1.0 Errata provides useful info on the working OSPI clock configurations.

The table under this i2249 note, lists the supported OSPI clocking topologies. For the QSPI flash memory which does not support DQS signal, only the highlighted options shall be valid. The TAP (No-PHY) DDR mode option highlighted in orange shall be valid when the AM67A ROM performs booting from the QSPI memory. The External Board Loopback with PHY topology is used to allow faster operations of QSPI  (custom bootloader or other operations with Flash memory). 

The two connectivity corresponding configurations are illustrated in the Section,  No Loopback, Internal PHY Loopback, and Internal Pad Loopback and Section, External Board Loopback of the Device Datasheet

As I refer to the schematic checklist tool from the: https://www.ti.com/jp/lit/an/sprad91b/sprad91b.pdf that you pointed, there is also another note which specifies the connectivity in case that data strobe output (DQS) not available from memory side. Please refer to the guidelines highlighted in yellow. According to the guideline the LBCLKO output shall be connected to the DQS input.  

 I hope these findings answer your questions.

Thanks

Kind Regards

Anastas Yordanov

Hi,

Thank you for your reply.

As I refer to the schematic checklist tool from the: https://www.ti.com/jp/lit/an/sprad91b/sprad91b.pdf that you pointed, there is also another note which specifies the connectivity in case that data strobe output (DQS) not available from memory side. Please refer to the guidelines highlighted in yellow. According to the guideline the LBCLKO output shall be connected to the DQS input.  

What I would like you to confirm is whether above content should be applied to QSPI as well.
Is my understanding that user should follow above content to case of QSPI correct ?

Best Regards,