SK-AM62-LP: Regarding Mcu_PerformReset functionality Issue

Hi Pradeep,

Pradeep R said:

But our expectation, it should perform complete reset which is equal to power off and on of the board. we need the SBL boot flow to start again and run our Application on R5 Core.

The MCU_PerformReset performs a warm reset of the entire SoC. The boot will start from SBL again and R5 application will be loaded again. Even though it is not a power off-on kind of reset, except for a few CTRL MMR registers that retain their values, everything else if reset.

Regards,

Nihar Potturu

Hello Nihar,

The MCU_PerformReset performs a warm reset of the entire SoC. The boot will start from SBL again and R5 application will be loaded again. Even though it is not a power off-on kind of reset, except for a few CTRL MMR registers that retain their values, everything else if reset

Feedback --> But this is not happening, the stack gets corrupted and goes into Exception.

Regards,

Pradeep R

Hello Nihar,

we tried the Reset Switches on the board

Among all the Switches in SK-AM62-LP , it was switch SW1 does the required and expected reset as shown below, But as per EVM user guide, it is written that Switch SW1 and SW2 bits [15:0] are used to set the SoC Boot mode which is contradictory because SW3 and SW4 are used as Boot modes. Can you please let us know what SW1 do? SO that we can try same from software side 

Regards,

Pradeep R

Hi Pradeep,

SW1 should perform the same kind of reset as Mcu_PerformReset. Can you tell me the value being finally written into the RST_CTRL register when the API is called.

Regards,

Nihar Potturu. 

Hello NIhar, 

But Mcu_PerformReset is not performing the same operation as expected as SW1

The value written is "0x60" as per below code

LLD_REG32_WR(&RSTADDR_MCU_CTRL_MMR->RST_CTRL, MCU_PERFORM_RESET_MASK); here MCU_PERFORM_RESET_MASK = 0x60

Regards,

Pradeep R

Hi Pradeep,

Can you try writing 0x6 instead of 0x60 to the RST_CTRL register. Writing 0x60 would cause some unexpected behavior if the MCU domain reset isolation is not enabled.

Regards,

Nihar Potturu

Hello NIhar, 

Even with 0x6 it is same behavior, After Mcu_PerformReset , the control is in SBL

Regards,

Pradeep R

Hello NIhar, 

#define rstaddr ((LLD_wkup_ctrl_mmr_cfg0Regs*)0x43000000U)
#define RSTADDR_MCU_CTRL_MMR ((LLD_mcu_ctrl_mmr_cfg0Regs*)0x04500000U)

Now as per Mcu driver RSTADDR_MCU_CTRL_MMR  is used, should we use rstaddr ?

Regards,

Pradeep R

Hello Nihar,

Also please find the image of R5 core from CCS when we attach after mcu perform reset

If we do Power off and On the board again then it works properly again.

Regards,

Pradeep R

Hello Pradeep,

Pradeep R said:

Now as per Mcu driver RSTADDR_MCU_CTRL_MMR  is used, should we use rstaddr ?

You can use either of them. That should not matter.

Pradeep R said:

Also please find the image of R5 core from CCS when we attach after mcu perform reset

It looks the SoC is stuck in boot rom code. Can you share the value of 0x43018178 register value when this happens.

Regards,

Nihar Potturu

Hello Nihar,

we tried both but still same behaviour.

The value at address  0x43018178 is 0x00500000 

Regards,

Pradeep R

Hello Nihar,

Should we unlock the MMR registers before performing reset operations.

Regards,

Pradeep R

Hi Nihar,

Please find attached Flash schematic as discussed.

QSPI Flash.pdf

BR,

Shubham

Hi Pradeep,

Before the call today, can you confirm if 0x4206FF is the value being written to the RST_CTRL register in the Mcu_PerformReset API. 

Regards,

Nihar Potturu

Hello Nihar,

As discussed in Call today

we have followed below reset sequence :

Fls_nor_reset();                     --> provided by customer
(void)Mcu_PerformReset();  

where as Mcu_PerformSoftSysReset is defined as

#define MCU_PERFORM_RESET_MASK                  ((uint32)0x06U)

LLD_REG32_WR(&RSTADDR_MCU_CTRL_MMR->RST_CTRL, MCU_PERFORM_RESET_MASK);

with this change SOC reset is working as expected.

Regards,

Pradeep R