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Original question:

AM620-Q1: Can AC21 pin be used to measure the number and duration of pulses?

AM620-Q1: Can AA2 pin(AM62x, ALW Package) be used to perform logic and operations on pwm?

owens shi
Intellectual 280 points
Part Number: AM620-Q1


Tool/software:

Hi.Team

   We need to perform a logical "and" operation on the output levels of pwm0 and pwm1 using the output signal of pmw2.

Can the output signal of pwm2 be connected to AA2 pin(AM62x, ALW Package) to achieve this function by using the EPWM_TZ_IN1 function?

  • 0
    TI__Mastermind 40020 points

    Hi Owens, can you explain to me a bit about how/where the AND operator is going to be implemented/used?

    As you might know, the EPWM_TZ_IN1 (TZ1) pin is part of the EPWM Trip-Zone submodule. This is one of the six trip-zone inputs available to monitor for system faults and use that input for taking actions, mostly by forcing the PWM outputs to a high-impedance state to shut down a power stage and raising a trip flag when there is a trip event. So, coming back to your query I am not sure how you are planning to use the Trip-zone module for creating an AND operation. Please let me know so I can better understand your idea.
    thank you,
    Paula
  • 0 in reply to Paula Carrillo
    Intellectual 280 points

    hi，Paula

      

    Background

    pwm0: Period 2us, output pwm0_channel B

    pwm1: Period 2us, output pwm1_channel A & B

    pwm2: Period 400us, output pwm2_channel B

    At the beginning of each cycle, pwm2 sends a sync signal to synchronize pwm0 and pwm1

    Requirement

    When pwm2_channel B outputs A low level, keep both pwm0_channel B and pwm1_channel A & B at a low level

    When pwm2_channel B outputs A high level, keep both pwm0_channel B and pwm1_channel A & B at a low level

    Implementation method

    --pwm2_channel B branches a branch to connect to EPWM_TZ_IN1

    --EPWM_TZ_IN1 low level is configured as A "trip signal", through which pwm0_channel B and pwm1_channel A & B are both at low levels

    -- When EPWM_TZ_IN1 is configured at A high level, pwm0_channel B and pwm1_channel A & B output normally

    thank you,
    Owens
  • 0 in reply to owens shi
    TI__Mastermind 40020 points

    Hi Owens, I think there is an error/typo in your requirements. But if I am understanding correctly, you should be able to use PWM2 ChB as EPWM_TZ_IN1 input.

    Let me check internally if there is any HW objections and come back to you.

    Thank you,

    Paula

  • 0 in reply to Paula Carrillo
    TI__Genius 17521 points

    Dear Paula.

    may I ask if you have any upate?

    Paula Carrillo said:

    Hi Owens, I think there is an error/typo in your requirements. But if I am understanding correctly, you should be able to use PWM2 ChB as EPWM_TZ_IN1 input.

    Let me check internally if there is any HW objections and come back to you.

    thanks a lot!

    yong

  • 0 in reply to Yong Zhang
    TI__Mastermind 40020 points

    Hi Owens, let me send another ping to a colleague.

    In the meantime, can you confirm below "Requirements are correct"

    owens shi said:

    Requirement

    When pwm2_channel B outputs A low level, keep both pwm0_channel B and pwm1_channel A & B at a low level

    When pwm2_channel B outputs A high level, keep both pwm0_channel B and pwm1_channel A & B at a low level

    thank you

    Paula

  • 0 in reply to Paula Carrillo
    Intellectual 280 points

    hi，Paula

     You're right. There was indeed a small clerical mistake。

    Here are the revised requirements：

    Requirement

    When pwm2_channel B outputs A low level, keep both pwm0_channel B and pwm1_channel A & B at a low level

    When pwm2_channel B outputs A high level, pwm0_channel B and pwm1_channel A & B output normally

    thank you,
    Owens

  • 0 in reply to owens shi
    TI__Mastermind 40020 points

    Thanks for clarifying. 

    Paula

  • 0 in reply to Paula Carrillo
    TI__Mastermind 40020 points

    Hi Owens, I got feedback from our HW expert. He pointed out to two things we need to pay attention to:

    - When TZ_IN1, you will not be able to have eMMC memory due to pin conflict.

    - When connecting SoC output to SoC input, care must be taken select balls powered with the same power rail or powered by rails connected to the same PMIC power output.

    Thank you,

    Paula