C66 most HPI like peripheral

I'd say the PCIe is the most likely candidate for this. 

Best Regards,

Chad

I breezed through the PCIe users guide, and it appeared to me that it has limited access windows into the memory space for the host processor to access. Hyperlink seemed to be the same with it's address translation unit.

I think you can choose the candidate based on two major perspectives:

1. The access configuration of the peripheral itself

2. The connectivity of the peripheral to other peripherals (memory endpoints or device registers) in the SoC level

We can take PCIe as an example:

1. The PCIe data space in C66x is 256MB, which is used for outbound transfer (C66x initializes the access to the external devices).

    If the external device or host initializes the access to the C66x via PCIe link, it is inbound transfer for C66x PCIe, which is dependent on the BAR/BAR mask registers and inbound translation registers (not the data space). The default BAR setup of PCIe in EP mode in the bootloader is 2GB for BAR2/3 and 2GB for BAR4/5 in 64-bit addressing mode, which could cover most of the device memory region without changing the setup (without CPU involvement).

    Please refer the PCIe use cases document for details as well.

2. PCIe master port could access most of the peripheral memory and registers in C66x. Please refer to the connection matrix tables in Chapter 4 in the data manual for details.

    Please also note that some device configuration registers are only allowed to be accessed in supervisor mode. You can switch the PCIe master port to be supervisor mode by programming the PCIe configuration first. The related E2E thread is as follows:

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/131840.aspx#480784

Hope it helps on your decision.

Sincerely,

Steven

Thanks for clearing up some of those PCIe details. It looked as though SRIO has the same amount of access as PCIe in the connection matrix table. It also looked as though SRIO did not have any address translation or access registers that PCIe had. But SRIO does need to be initialized by the core where as PCIe can be initialized by the boot loader?