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Questions re SYS/BIOS and Code Composer

Steve Mitropoulos
Prodigy 100 points

I have some questions about SYS/BIOS and Code Composer. Perhaps you  can point me in the right direction for answers.

>> The version of Code Composer (v5) delivered with our TMDXEVM6678LE

>> development board is one version newer than the version used in both

>> the TI online documentation and the RTSC Wiki. There seems to be

>> major changes in how the XDC tools work with Code Composer. I have gone

>> through all of the tutorials and the course material for the SYS/BIOS

>> workshop but have not found how to use XDC with CCv5.

 Where can I find out how to configure SYS/BIOS using the new method

 of using the XDC tools? For example, I have tried to add a new task to

>> the .cfg file of the message_multicore demo. It seems like this

>> should be easy to do, and Code Composer lets me define one but then deletes

>> my addition and gives a cryptic (to me) error message:

>> xdc.MODULE_NOT_FOUND: xdc.module: no module named 'tsk1' in the

>> package xconfig_message_multicore The package

>> xconfig_message_multicore doesn't seem to be defined anywhere and the

>> existing "tsk0" is only defined in the .cfg and .c files.

>>

>> The multi-processor examples all seem to put all of their code in L2,

>> using external memory only for data. We have multiple algorithms that

>> each take most of the L2 space. Our plan is to use the MessageQ

>> facility communicate between cores and put the SYS/BIOS code for each

>> core into external memory. There does not seem to be an example of

>> how  to use a link command file (or an RTSC facility) to do this. Where

>> can  I find such an example.

  • 0
    TI__Mastermind 26780 points

    Steve,

    For the first point, there is a very similar thread here:
    http://e2e.ti.com/support/embedded/bios/f/355/t/156948.aspx#570487

    For an example of how to place SYS/BIOS sections into specific memory regions, please see section 6.3 "Placing Sections into Memory Segments" in Bios_User_Guide.pdf.  (This file is in the "docs" subdirectory of your SYS/BIOS installation).

    Scott

  • 0 in reply to ScottG
    Prodigy 100 points

    Thank you Scott.

     

     

  • 0 in reply to ScottG
    Prodigy 100 points

    Hi Scott,

    Here is the response from the customer..--------

    ----------------------------------------------------------------------------------------------

    Thanks for the pointer. That's actually section 5.3 in the

    bios_6_31_04_27 user guide.

    That chapter shows how to place sections into memory segments for a

    single processor. I am interested in an example of allocating memory in

    a multi-core C6678 where code for each core has to be assigned to

    different addresses in external memory. That means that the placement in

    separate linker command files or .cfg files has to be coordinated

    between separate projects in the workspace. The segments have to be

    non-overlapping.

    How do I define these different memory segments in the .cfg file? Do I

    have to bypass the .cfg file and create separate linker command files by

    hand? Is there another way to do this that I don't know about?

  • 0 in reply to Steve Mitropoulos
    TI__Mastermind 37985 points

    Steve,
    there are two threads with similar questions. In the first one, http://e2e.ti.com/support/embedded/bios/f/355/t/149682.aspx, the user says he succeeded in changing the memory map in the cfg script, but I am not sure how he did it because he did not post the details.

    In another thread I described a solution that requires multiple platforms and multiple projects that each uses a different platform, http://e2e.ti.com/support/embedded/bios/f/355/t/145752.aspx. Please take a look at these threads and let us know if multiple platforms work for you, and if you have any further questions.