• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 101 subscribers
  • Views 1830 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PRU Shared Memory when using SYS/BIOS

Thomas Mitchell
Intellectual 610 points
Other Parts Discussed in Thread: AM1808, SYSBIOS

I'm trying to use the PRU in the AM1808 to perform some dedicated I/O functions. When I am not using SYS/BIOS as an OS on the AM1808 the PRU is able to share L3 and DDR memory with the AM1808, but when I am running under SYS/BIOS the PRU cannot always write to L3 and/or DDR memory.

In the PRU I have the following instruction;

SBBO  io.data, BufPtr, 0, 0x02 // Save LSB & MSB

The expected result is that when this instruction is executed in the PRU the PRU writes 2 bytes from io.data to the address in BufPtr. If I am running my app under SYS/BIOS the above PRU instruction may or may not work. When BufPtr contains some valid memory locations (example 0x80009290) it will not write the data from io.data as expected. Changing the contents of BufPtr to some other valid memory location (example 0x8000870C) and then the byte transfer may or may not work. The success is sometimes intermittently. To verify that the data transfer took place I am using the memory view and watch feature in CCS after the PRU has completed the operation. If I perform the same PRU function without using an application that uses SYS/BIOS the PRU functions as expected all the time.

Are there special considerations in the set up of SYS/BIOS to allow the PRU to share L3 and/or DDR memory with the AM1808? Are any special MMU setups required?

 

  • 0
    TI__Expert 4125 points

    Could it be a cache issue? SYS/BIOS enables the cache on the ARM, so if the PRU writes to external memory (DDR), you will need to bump the cache so the ARM sees the data.

    Mark

     

  • 0 in reply to MarkGrosen
    Intellectual 610 points

    Mark,

    It does appear to be a cache issue. When I include the SYS/BIOS call Cache_disable(Cache_Type_ALLD) or Cache_disable(Cache_Type_ALL) the intermittent memory writing problem does not happen. The code in the PRU functions as expected.

    To "bump" the cache prior to the ARM reading the memory locations I added the call Cache_inv(blockPtr, byteCnt, Cache_Type_ALL,true). Adding this call did not fix the problem.

    Is there anyway to disable the cache on a block of memory? From the information in the SYS/BIOS users guide it appears that I can disable cache for all of memory, all of program memory or all of data memory but not for a specific range of memory. At this point my only solution is to disable cache for all data memory to get the PRU to work correctly.

     

  • 0 in reply to Thomas Mitchell
    TI__Mastermind 20805 points

    Thomas --

    You can map certain regions as non-cacheable using the MMU.   The ti.sysbios.family.arm.arm9.Mmu module should be useful for you.

    Check the API documentation for details.   You can get to the API docs via the Eclipse help system table of contents or via link in the release note.

    It is easy to work with the 1Mbyte pages with the first level MMU descriptors.  If you need finer resolution, you can use the 2nd level descriptors.  You might have to consult some Arm docs or google around for help with the 2nd-level descriptors.  The API docs for the Mmu module have a couple examples that should help.

    Regards,
    -Karl-

  • 0
    TI__Mastermind 32475 points

    Thomas,

    What version of SYSBIOS are you using?

    For the arm9 Cache, Data caching requires the MMU to be enabled and the cacheable attribute of the section/page descriptor for a corresponding memory region to be enabled.  Also the cache line size is 32 bytes.

    Judah

  • 0 in reply to judahvang
    Intellectual 610 points

    Judah,

    I'm currently using SYS/BIOS ver 6.32.5.54.

    Currently the MMU is enabled in SYS/BIOS. The shared memory between the PRU and ARM is currently not in a predefined memory location. The buffer var is defined in the app and the linker is assigning a location. To have the MMU exclude the portion of memory assigned to the buffer I will need to either have the linker place the buffer in a predefined memory location or be able to dynamically alter the MMU (rather than in the cfg file) while the program is running and after the location of the buffer has been determined.

    How do I dynamically alter the MMU? Alternatively. how do I define a memory location for a group of variables to the linker?

  • 0 in reply to Thomas Mitchell
    TI__Mastermind 32475 points

    Thomas,

    That's a recent release of SYSBIOS so it should be good.  Older versions of SYSBIOS may have had some issues with the arm9 Cache.

    You can dynamically change the Mmu settings with the ti/sysbios/family/arm/arm9/Mmu module APIs.

    For the second question:

      1.   You need to define your own linker command file which contains the additional MEMORY SECTIONS that you need.

                       MEMORY
                       {
                                   MYSECT (RWX): origin = 0x200000,   length = 0x400
                       }

      2.   In your *.c file you need to place your variables into an output section.  For example:

                      #pragma DATA_SECTION(myBuf, ".myBufsect");

                      UInt32 myBuf[32];

      3.  In your linker command file you need to place your output section into your MEMORY SECTION

                      SECTIONS {

                              .myBufsect: load > MYSECT

                      }

    Judah