Tool/software:
I'm working on reading two ADS7038Q ADCs simultaneously on an AM6422 processor. The idea is to use a shared clock configuration where MCSPI0 acts as the master and provides the clock signal for both itself and MCSPI1. Unfortunately, I'm getting corrupted data and it seems to be due to synchronization issues between the two MCSPI peripherals.
What I'm Trying to Achieve
The goal is to read both ADCs in perfect synchronization using:
- One SPI clock (generated by MCSPI0) that's shared by both peripherals
- A single chip select GPIO connected to all components - both ADCs and both MCSPIs
- Parallel data lines, with each ADC having its own MISO connection back to its respective MCSPI
Hardware Setup
I'm using an AM6422 processor with two ADS7038Q ADCs. For the clock architecture, MCSPI0 is configured as master and generates the SPI clock, while MCSPI1 is configured as a slave that should use MCSPI0's clock. The same physical clock line is connected to both ADCs and to MCSPI1's clock input.
For chip select, I have a single GPIO that connects to:
- Both ADCs' CS pins
- MCSPI0's CS input
- MCSPI1's CS input
All four CS connections share this same signal. The data lines are kept separate with MISO from ADC1 going to MCSPI0 and MISO from ADC2 going to MCSPI1.
Current Implementation
I've configured MCSPI0 as the SPI master to generate the clock, and MCSPI1 as a slave so it won't generate its own clock but should instead sample data using MCSPI0's clock signal. Both MCSPIs are configured to use interrupt mode for the transfers.
My transaction sequence works like this:
- Assert the shared CS (pull GPIO low) - this signals all four components
- Start both MCSPI_transfer calls in interrupt mode
- Wait for both transfers to complete using semaphores (triggered by the interrupt callbacks)
- De-assert CS (pull GPIO high) to release all components
The Core Issue
The problem is that I can't get MCSPI1 to reliably use MCSPI0's clock signal. Even with various timing adjustments, the two peripherals don't stay synchronized. This results in:
- Corrupted or inconsistent ADC readings
- Different values from the ADCs on each read cycle
- Apparent timing misalignment between clock and data sampling
So my main question is: Is it actually possible for MCSPI peripherals on the AM6422 to share a clock signal like this? Is there a specific configuration or method to make MCSPI1 properly use an external clock from MCSPI0? Or am I trying to do something that the hardware simply doesn't support?
Any insights would be really appreciated
