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DRA821U: How to check if processor is working properly.

Santiago Pérez
Prodigy 160 points

Part Number: DRA821U
Other Parts Discussed in Thread: DRA821, UNIFLASH

Tool/software:

Hi,

We have a custom board with DRA821U.

We are having problems with the initial booting following this application note: spradc5.

We have the same PMIC as the Evaluation Kit (slvuby7a).

We have checked that all signals are working as provide in datasheet Figure 7-3:

We put bootmode pins into DFU mode, to try to check if the processor try to boot in DFU mode, but the host PC didn´t detect the DFU target (spracy5).

We are not sure about how to check if the processor is at least booting and running DMSC ROM code and MCU ROM code.

The idea behind booting in DFU mode was to check that at least MCU ROM code was running. 

What would be the ideal way to debug the boot processor in this stage of our design?

Thank in advance,
Santi

  • 0
    TI__Guru*** 132231 points

    Hi,

    TI resource assigned to this post, is currently out of office, please be aware that there will be a delay in response.

    Regards,

    kb

  • +1 in reply to KB
    TI__Guru**** 170530 points

    Hello Santi,

    I have a few questions which will help us understand better: 

    • Which SDK version is being used? 
    • What other boot modes can be tried? 
    • What's the console UART on your custom board? 
    • Do you have access to debugger? If yes can you connect to MCU r5f?

    Best Regards,

    Keerthy 

  • 0 in reply to Keerthy J
    Prodigy 160 points

    Sorry i miss clicked the button "resolved my issue".

    In relation to you quesitons:

    - We are using "ti-processor-sdk-linux-j7200-evm-11_00_10_01"

    - We can try, DFU, SD and UART boot mode, but we just have acces to MCU UART.

    - Console UART is going to be MCU_UART.

    - Im not sure about debugger, i will confirm with the HW engineer. By the way, lets say we have access, how would this affect?  

  • 0 in reply to Keerthy J
    Prodigy 160 points

    Hi!

    Thanks for your answer!

    So best way to do this initial check is to boot in UART MODE using this MCU UART?

    Ideally which option would be the ideal for this kind of debug? CSS and JTAG connector? Or it just fine with MCU_UART?

  • 0 in reply to Santiago Pérez
    TI__Guru**** 170530 points

    You can start with changes in device tree for MCU UART and use CCS jtag for debug.

    Best Regards,

    Keerthy 

  • 0 in reply to Keerthy J
    Prodigy 160 points

    Hi Kerthy, 

    Thanks for your suggestion. We are booting in UART mode and have updated the DTS to use only MCU_UART (we verified this setup on the EVM).

    We are able to boot tiboot3.bin via MCU_UART, but on our custom board we get the following logs:

    U-Boot SPL 2025.01-ti-gac2433f99366-dirty (Oct 06 2025 - 12:51:40 +0200)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -121
Timeout during frequency handshake
### ERROR ### Please RESET the board ###

    We’re not entirely sure what this error indicates.
    Is it possible to enable additional trace or logging options to get more detailed debug information?

    Also, could you please share the steps to perform debugging using CSS JTAG?

    Thanks for your help,

    Santi

  • 0 in reply to Santiago Pérez
    TI__Guru**** 170530 points

    Hello Santi,

    Do you have a different DDR part on your custom board? This seems like DDR is unable to init properly.

    Best Regards,

    Keerthy

  • 0 in reply to Keerthy J
    Prodigy 160 points

    Hi Keerthy,

    Yes we have a different DDR part becouse we look for the one that is mounted in the j7200 EVM (MT53D1024M32D4DT-046 AAT:D) and is End of Life.

    We select and have mounted in our custom board this one: MT53E512M32D1ZW-046 AUT:B.

    We are not really sure about how to config this new DDR. 

  • 0 in reply to Santiago Pérez
    TI__Mastermind 44160 points

    Hi,

    The part you have mounted appears to be a single rank memory, whereas the part on the J7200 EVM is a dual rank memory. If using the default TI EVM DDR register configuration, the DDR initialization is likely timing out while trying to train the second rank (which doesn't exist for your selected memory).

    You can customize the DRA821 DDR register settings using the DDR register configuration tool, located here: https://dev.ti.com/sysconfig/?product=TDA4x_DRA8x_AM67x-AM69x_DDR_Config&device=J7200_DRA821_SR1.0_alpha

    From the default tool values, you would need to change "Chip Selects / Ranks" from a value of 2 to a value of 1. Other values would likely be OK to keep as the default. I have gone ahead and generated these files for you with the chip select / rank change. Can you try to use the associated file in your software build and see if that resolves your issue?

    DRA821_MT53E512M32D1ZW.zip

    Thanks,
    Kevin

  • 0 in reply to Kevin S
    Prodigy 160 points

    Hi Kevin!

    Hi Kevin,

    Thanks for your help! The .zip file you sent works, we were able to send the tiboot3.spl and tispl.bin successfully.

    It seems that with this configuration the DDR is working properly, but we’ve encountered another issue before loading U-Boot. You can see it in the following logs:

    U-Boot SPL 2025.01-ti-gac2433f99366-dirty (Oct 07 2025 - 15:09:04 +0200)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -121
Trying to boot from UART
CCdevice
Skipping authentication on GP device
Skipping authentication on GP device
Skipping authentication on GP device
Skipping authentication on GP device
Loaded 1064483 bytes
Loading Environment from nowhere... OK
init_env from device 7 not supported!
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.12.0(release):11.00.09-dirty
NOTICE:  BL31: Built : 15:51:25, Oct  2 2025

U-Boot SPL 2025.01-ti-gac2433f99366-dirty (Oct 07 2025 - 15:08:41 +0200)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
single-pinctrl pinctrl@4301c068: configuring pins for wkup-i2c0-default-pins
single-pinctrl pinctrl@4301c068:   reg/val 80477af8a/0x00060000
single-pinctrl pinctrl@4301c068:   reg/val 80477af8a/0x00060000
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -121
single-pinctrl pinctrl@4301c068: configuring pins for wkup-gpio-default-pins
single-pinctrl pinctrl@4301c068:   reg/val 81fffc88a/0x00050007
single-pinctrl pinctrl@4301c000: 13 pins
single-pinctrl pinctrl@4301c000: configuring pins for mcu-fss0-hpb0-default-pins
single-pinctrl pinctrl@4301c000:   reg/val 81fffcc8a/0x00010001
single-pinctrl pinctrl@4301c000:   reg/val 81fffcc8a/0x00010001
single-pinctrl pinctrl@4301c000:   reg/val 81fffcc8a/0x00010001
single-pinctrl pinctrl@4301c000:   reg/val 81fffcc8a/0x00010001
single-pinctrl pinctrl@4301c000:   reg/val 81fffcc8a/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 81fffcc8a/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 81fffcc8a/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 81fffcc8a/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 81fffcc8a/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 81fffcc8a/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 81fffcc8a/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 81fffcc8a/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 81fffcc8a/0x00050001
idle-states

    We’re currently using the default Device Tree for the EVM; we haven’t optimized it yet since we first want to verify that we can boot our custom board with this configuration.

    We also tried removing the SERDES configuration because we thought it might be causing the “idle-state” issue, but the behaviur is the same. However, when reaching this state, the processor resets after a while.

    What this "idle-state" means and, how can we solve it? 

    An which point of the u-boot diagram boot flow are we currently stuck? Are we stuck in OP-TEE? Before this? We are not sure:


    Thanks for the help.

  • 0 in reply to Santiago Pérez
    TI__Mastermind 44160 points

    Hi Santiago,

    Thanks for the additional information and confirming that you have been able to progress further in the boot procedure.

    I'll re-assign the ticket back to our software team who should be able to help further.

    Regards,
    Kevin

  • 0 in reply to Kevin S
    TI__Guru**** 170530 points

    Hi Santi,

    EEPROM i believe is not present on your custom board? I am yet to dig deeper into idle states.
    Do you have a debugger? Is A72 hanging at U-Boot stage?

    - Keerthy

  • 0 in reply to Keerthy J
    Prodigy 160 points

    Hi Keerthy,

    Yes, that’s correct our custom board doesn’t have an EEPROM, so we’re unable to read the device ID. Could this be an issue? Is the board revision detection required for the boot process to continue?

    At the moment, we don’t have a debugger available for the custom board (there’s no connector or routed traces to the processor). However, it seems like this will be necessary in the future, so we’re planning to include a connector in the next PCB revision.

    We do have the J7200 EVM, but we haven’t tried using the debugger integrated with the J721E EVM yet. Could you please guide us on how to get started with the debugger on the EVM? Also, would it be possible to reproduce the same boot failure on the EVM while using the debugger?

    Keerthy J said:
    Is A72 hanging at U-Boot stage?

    No, it’s not. We’re uploading all the .bin files through UART, but we never reach the stage where u-boot.img is ask to be loaded, so it’s getting stuck at tispl.bin.

    Thanks a lot for the support.

    Best regards,
    Santi

  • 0 in reply to Santiago Pérez
    TI__Guru**** 170530 points

    Hello Santi,

    git diff board/ti/j721e/evm.c 
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 11635d3d..c7affd37 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -455,6 +455,7 @@ static void setup_serial(void)
 
 int board_late_init(void)
 {
+       return 0;
        if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
                setup_board_eeprom_env();
                setup_serial();
@@ -467,7 +468,6 @@ int board_late_init(void)
        if (board_is_j721e_som())
                configure_serdes_sierra();
 
-       return 0;
 }
 #endif

    Let me know if the above bypassing the late init helps on custom board as that is only relevant to EVM.

    - Keerthy

  • 0 in reply to Keerthy J
    Prodigy 160 points

    Hi Kerthy,

    Thanks for the suggestion.

    I’ve tried the patch you suggested, but we’re still stuck at the same point.
    Below are the logs related to this modification:


    01000000011a00006a3776636c00000000000000475020200000020000000200CC
U-Boot SPL 2025.01-ti-gac2433f99366-dirty (Oct 07 2025 - 15:36:16 +0200)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -121
Trying to boot from UART
CCCCCCCCCC
          Skipping authentication on GP device
Skipping authentication on GP device
Skipping authentication on GP device
Skipping authentication on GP device
Loaded 1042747 bytes
Loading Environment from nowhere... OK
init_env from device 7 not supported!
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.12.0(release):11.00.09-dirty
NOTICE:  BL31: Built : 15:51:25, Oct  2 2025

U-Boot SPL 2025.01-ti-gac2433f99366-dirty (Oct 09 2025 - 14:27:55 +0200)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -121
idle-states


    As you can see, we’re still getting stuck at the same stage after applying the changes, so it seems the patch doesn’t have any effect.

    When the “idle-states” log appears, the system freezes and we cannot load the next stage (u-boot.img).

    Just to remind you in case it’s relevant we are loading all the boot files through the MCU UART.

    Thanks,
    Santi

  • 0 in reply to Santiago Pérez
    TI__Guru**** 170530 points

    Hello Santi,

    Does the core crash after this? Are you able to attach a debugger and see if this is crashed or a loop?

    EEPROM not available at 0x50, trying to read at 0x51
    Reading on-board EEPROM at 0x51 failed -121

    We can comment that out as well:

    diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c

index 11635d3d..33796afa 100644

--- a/board/ti/j721e/evm.c

+++ b/board/ti/j721e/evm.c

@@ -179,6 +179,8 @@ int do_board_detect(void)

 

 int checkboard(void)

 {

+       return 0;

+

        struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;

 

        if (do_board_detect())

@@ -455,6 +457,7 @@ static void setup_serial(void)

 

 int board_late_init(void)

 {

+       return 0;

        if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {

                setup_board_eeprom_env();

                setup_serial();

@@ -467,7 +470,6 @@ int board_late_init(void)

        if (board_is_j721e_som())

                configure_serdes_sierra();

 

-       return 0;

 }

 #endif

    - Keerthy

  • 0 in reply to Keerthy J
    Prodigy 160 points

    Hi Kerthy, 
    I will try this new suggestion and give some feedback.

    Just to confirm, these changes should take effect in the new builds just by running make u-boot, right? Or is there anything else I need to do?

    We’re not able to attach an external debugger; we only have access to the integrated debugger on the J7200 EVM.

    Is it possible to use the EVM debugger with our custom board?

    Also, we’re not entirely sure how to use this debugger during the boot process. I found some information about CCS and debugging here, but I don’t fully understand the procedure, and I haven’t been able to debug the boot process on the EVM. Could you please share some guidance or documentation on how to debug this boot sequence?

    Thanks,
    Santi

  • 0 in reply to Santiago Pérez
    Prodigy 160 points

    Hi Kerthy,

    I have added your suggestion and nothing have changed. Here you can see the logs with the suggestion:

    00CC01000000011a00006a3776636c00000000000000475020200000020000000200CC                               |
U-Boot SPL 2025.01-ti-gac2433f99366-dirty (Oct 14 2025 - 14:40:15 +0200)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
Esta traza es nuestra
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -121
Trying to boot from UART
CCCCCCCCCe
Skipping authentication on GP device
Skipping authentication on GP device
Skipping authentication on GP device
Skipping authentication on GP device
Loaded 1064507 bytes
Loading Environment from nowhere... OK
init_env from device 7 not supported!
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.12.0(release):11.00.09-dirty
NOTICE:  BL31: Built : 15:51:25, Oct  2 2025

U-Boot SPL 2025.01-ti-gac2433f99366-dirty (Oct 14 2025 - 14:39:52 +0200)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
single-pinctrl pinctrl@4301c068: configuring pins for wkup-i2c0-default-pins
single-pinctrl pinctrl@4301c068:   reg/val 80477af8a/0x00060000
single-pinctrl pinctrl@4301c068:   reg/val 80477af8a/0x00060000
Esta traza es nuestra
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -121
single-pinctrl pinctrl@4301c068: configuring pins for wkup-gpio-default-pins
single-pinctrl pinctrl@4301c068:   reg/val 81fffc08a/0x00050007
single-pinctrl pinctrl@4301c000: 13 pins
single-pinctrl pinctrl@4301c000: configuring pins for mcu-fss0-hpb0-default-pins
single-pinctrl pinctrl@4301c000:   reg/val 81fffc48a/0x00010001
single-pinctrl pinctrl@4301c000:   reg/val 81fffc48a/0x00010001
single-pinctrl pinctrl@4301c000:   reg/val 81fffc48a/0x00010001
single-pinctrl pinctrl@4301c000:   reg/val 81fffc48a/0x00010001
single-pinctrl pinctrl@4301c000:   reg/val 81fffc48a/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 81fffc48a/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 81fffc48a/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 81fffc48a/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 81fffc48a/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 81fffc48a/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 81fffc48a/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 81fffc48a/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 81fffc48a/0x00050001
Previo a idle-states
mux-controller@47000004
idle-states
POST idle-states

    We have added some traces as you can see, just to be sure we were compiling right the files...

    diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 11635d3d..19de84c5 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -164,6 +164,7 @@ int do_board_detect(void)
 
        ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
                                         CONFIG_EEPROM_CHIP_ADDRESS);
+       printf("Esta traza es nuestra\n");                                       
        if (ret) {
                printf("EEPROM not available at 0x%02x, trying to read at 0x%02x\n",
                       CONFIG_EEPROM_CHIP_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS + 1);
@@ -178,16 +179,18 @@ int do_board_detect(void)
 }
 
 int checkboard(void)
-{
+{      
+       return 0;
        struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
 
        if (do_board_detect())
                /* EEPROM not populated */
+               
                printf("Board: %s rev %s\n", "J721EX-PM1-SOM", "E2");
        else
                printf("Board: %s rev %s\n", ep->name, ep->version);
 
-       return 0;
+       // return 0;
 }
 
 /*

    We also put a trace on mmio.c, as we see this "idle-states" logs come from here, here you can see the "traces" we put related with the above output:

    diff --git a/drivers/mux/mmio.c b/drivers/mux/mmio.c
index e06f4462..6c262092 100644
--- a/drivers/mux/mmio.c
+++ b/drivers/mux/mmio.c
@@ -90,12 +90,15 @@ static int mmio_mux_probe(struct udevice *dev)
                return -ENOMEM;
 
        ret = dev_read_u32_array(dev, "idle-states", idle_states, num_fields);
+       printf("Previo a idle-states\n");
+       
        if (ret < 0) {
+               printf("%s\n", dev->name);
                log_err("idle-states");
                devm_kfree(dev, idle_states);
                idle_states = NULL;
        }
-
+       printf("\nPOST idle-states\n");
        for (i = 0; i < num_fields; i++) {
                struct mux_control *mux = &mux_chip->mux[i];
                struct reg_field field;

  • +1 in reply to Santiago Pérez
    TI__Guru**** 170530 points

    I think i found the culprit thanks to the detailed logs.

    Patch:

    iff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c

index 11635d3d..449d1f0b 100644

--- a/board/ti/j721e/evm.c

+++ b/board/ti/j721e/evm.c

@@ -179,6 +179,8 @@ int do_board_detect(void)

 

 int checkboard(void)

 {

+       return 0;

+

        struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;

 

        if (do_board_detect())

@@ -455,6 +457,7 @@ static void setup_serial(void)

 

 int board_late_init(void)

 {

+       return 0;

        if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {

                setup_board_eeprom_env();

                setup_serial();

@@ -467,7 +470,6 @@ int board_late_init(void)

        if (board_is_j721e_som())

                configure_serdes_sierra();

 

-       return 0;

 }

 #endif

 

@@ -535,18 +537,4 @@ void spl_board_init(void)

                if (ret)

                        printf("ESM PMIC init failed: %d\n", ret);

        }

-       if ((IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM) || IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM)) &&

-           IS_ENABLED(CONFIG_HBMC_AM654)) {

-               struct udevice *dev;

-               int ret;

-

-               ret = detect_SW3_1_state();

-               if (ret == 1) {

-                       ret = uclass_get_device_by_driver(UCLASS_MTD,

-                                                         DM_DRIVER_GET(hbmc_am654),

-                                                         &dev);

-                       if (ret)

-                               debug("Failed to probe hyperflash\n");

-               }

-       }

 }

    Clue: 

    single-pinctrl pinctrl@4301c000: configuring pins for mcu-fss0-hpb0-default-pins

    This gave me a clue for Hyperbus. Mostly on your board this is getting probed while not being present.

    Let me know if this helps. Since I have no way to reproduce this issue, I will need your help to test.

    - Keerthy

  • 0 in reply to Keerthy J
    Prodigy 160 points

    Hi Kerthy,

    You were right!
    With your suggestion, we managed to reach the stage where u-boot.img is loaded. You can see it in this log:

    a00006a3776636c00000000000000475020200000020000000200CCCCCCCCCCCCCCCCCC
U-Boot SPL 2025.01-ti-gac2433f99366-dirty (Oct 16 2025 - 12:21:50 +0200)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
Esta traza es nuestra
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -121
Trying to boot from UART
CCCe
Skipping authentication on GP device
Skipping authentication on GP device
Skipping authentication on GP device
Skipping authentication on GP device
Loaded 1064115 bytes
Loading Environment from nowhere... OK
init_env from device 7 not supported!
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.12.0(release):11.00.09-dirty
NOTICE:  BL31: Built : 15:51:25, Oct  2 2025

U-Boot SPL 2025.01-ti-gac2433f99366-dirty (Oct 16 2025 - 12:21:26 +0200)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
single-pinctrl pinctrl@4301c068: configuring pins for wkup-i2c0-default-pins
single-pinctrl pinctrl@4301c068:   reg/val 80477af8a/0x00060000
single-pinctrl pinctrl@4301c068:   reg/val 80477af8a/0x00060000
Esta traza es nuestra
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -121
Trying to boot from UART
CCC01000000011a00006a3776636c00000000000000475020200000020000000200CCCC
U-Boot SPL 2025.01-ti-gac2433f99366-dirty (Oct 16 2025 - 12:21:50 +0200)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
Esta traza es nuestra
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -121
Trying to boot from UART
CCvice
Skipping authentication on GP device
Skipping authentication on GP device
Skipping authentication on GP device
Skipping authentication on GP device
Loaded 1064115 bytes
Loading Environment from nowhere... OK
init_env from device 7 not supported!
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.12.0(release):11.00.09-dirty
NOTICE:  BL31: Built : 15:51:25, Oct  2 2025

U-Boot SPL 2025.01-ti-gac2433f99366-dirty (Oct 16 2025 - 12:21:26 +0200)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
single-pinctrl pinctrl@4301c068: configuring pins for wkup-i2c0-default-pins
single-pinctrl pinctrl@4301c068:   reg/val 80477af8a/0x00060000
single-pinctrl pinctrl@4301c068:   reg/val 80477af8a/0x00060000
Esta traza es nuestra
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -121
Trying to boot from UART
CCCdevice
Skipping authentication on GP device
Loaded 1318315 bytes
single-pinctrl pinctrl@4301c068: configuring pins for wkup-gpio-default-pins
single-pinctrl pinctrl@4301c068:   reg/val 81fffc88a/0x00050007


U-Boot 2025.01-ti-gac2433f99366-dirty (Oct 16 2025 - 12:21:26 +0200)

SoC:   J7200 SR2.0 GP
Model: Texas Instruments J7200 EVM
DRAM:  2 GiB (total 4 GiB)
Previo a idle-states

POST idle-states
Previo a idle-states

POST idle-states
ti_sci system-controller@44083000: ti_sci_of_to_info: Acquiring notify channel failed. ret = -61
single-pinctrl pinctrl@4301c068: 59 pins
single-pinctrl pinctrl@4301c068: configuring pins for mcu-uart0-default-pins
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c0f8/0x00050000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c0fc/0x00010000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c0f4/0x00050000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c0f0/0x00010000
Core:  109 devices, 32 uclasses, devicetree: separate
Flash: single-pinctrl pinctrl@4301c000: 13 pins
single-pinctrl pinctrl@4301c000: configuring pins for mcu-fss0-hpb0-default-pins
single-pinctrl pinctrl@4301c000:   reg/val 0x000000004301c000/0x00010001
single-pinctrl pinctrl@4301c000:   reg/val 0x000000004301c004/0x00010001
single-pinctrl pinctrl@4301c000:   reg/val 0x000000004301c02c/0x00010001
single-pinctrl pinctrl@4301c000:   reg/val 0x000000004301c030/0x00010001
single-pinctrl pinctrl@4301c000:   reg/val 0x000000004301c008/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 0x000000004301c00c/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 0x000000004301c010/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 0x000000004301c014/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 0x000000004301c018/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 0x000000004301c01c/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 0x000000004301c020/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 0x000000004301c024/0x00050001
single-pinctrl pinctrl@4301c000:   reg/val 0x000000004301c028/0x00050001
Previo a idle-states
mux-controller@47000004
idle-states
POST idle-states
"Error" handler, esr 0xbf000002
elr: 000000008085739c lr : 000000008085733c (reloc)
elr: 00000000ffef839c lr : 00000000ffef833c
x0 : 00000000fde87fe0 x1 : 0000000000000000
x2 : 0000000000000019 x3 : 0000000500000000
x4 : 0000000000000004 x5 : 0000000000000000
x6 : 0000000000000004 x7 : 0000000000000004
x8 : 0000000000000006 x9 : 00000000fde88110
x10: 0000000000000000 x11: 0000000000000002
x12: 0000000000000018 x13: 00000000fde68bc0
x14: 0000000000000008 x15: 00000000fde684ab
x16: 00000000fff06424 x17: 0000000000000000
x18: 00000000fde80e00 x19: 00000000fde830d0
x20: 0000000000000000 x21: 00000000fde87fe0
x22: 00000000fffa9d98 x23: 000000007f6a1000
x24: 0000000000000007 x25: 0000000000000000
x26: 00000000800bd17a x27: 00000000800bd000
x28: 00000000800bd162 x29: 00000000fde689e0

Code: 14000016 f9400003 79404065 12003ca5 (d5033fbf)
Resetting CPU ...

resetting ...

    As you can see, when booting U-Boot we are still getting the same Hyperbus failure.
    We don’t understand why this happens in U-Boot, since we commented out the function you suggested.
    Could there be a different .c source used at this stage of U-Boot? If so, where is it located and how can we modify it?

    We found that setting CONFIG_HBMC_AM654=n allowed us to proceed further, this seems to match your suggestion that this config could be adjusted. We’re not entirely sure if this is the best approach, though.

    After applying CONFIG_HBMC_AM654=n, we reached this stage:

    U-Boot SPL 2025.01-ti-gac2433f99366-dirty (Oct 16 2025 - 13:17:56 +0200)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
Esta traza es nuestra
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -121
Trying to boot from UART
CCC
Skipping authentication on GP device
Skipping authentication on GP device
Skipping authentication on GP device
Skipping authentication on GP device
Loaded 1062899 bytes
Loading Environment from nowhere... OK
init_env from device 7 not supported!
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.12.0(release):11.00.09-dirty
NOTICE:  BL31: Built : 15:51:25, Oct  2 2025

U-Boot SPL 2025.01-ti-gac2433f99366-dirty (Oct 16 2025 - 13:17:33 +0200)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
single-pinctrl pinctrl@4301c068: configuring pins for wkup-i2c0-default-pins
single-pinctrl pinctrl@4301c068:   reg/val 80477af8a/0x00060000
single-pinctrl pinctrl@4301c068:   reg/val 80477af8a/0x00060000
Esta traza es nuestra
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -121
Trying to boot from UART
CCCCCCCCCC  device                                                                                 |
Skipping authentication on GP device
Loaded 1316971 bytes
single-pinctrl pinctrl@4301c068: configuring pins for wkup-gpio-default-pins
single-pinctrl pinctrl@4301c068:   reg/val 81fffc88a/0x00050007


U-Boot 2025.01-ti-gac2433f99366-dirty (Oct 16 2025 - 13:17:33 +0200)

SoC:   J7200 SR2.0 GP
Model: Texas Instruments J7200 EVM
DRAM:  2 GiB (total 4 GiB)
Previo a idle-states

POST idle-states
Previo a idle-states

POST idle-states
ti_sci system-controller@44083000: ti_sci_of_to_info: Acquiring notify channel failed. ret = -61
single-pinctrl pinctrl@4301c068: 59 pins
single-pinctrl pinctrl@4301c068: configuring pins for mcu-uart0-default-pins
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c0f8/0x00050000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c0fc/0x00010000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c0f4/0x00050000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c0f0/0x00010000
Core:  107 devices, 31 uclasses, devicetree: separate
Flash: 0 Bytes
MMC:   am654_sdhci mmc@4f80000: Couldn't find ti,otap-del-sel-mmc-hs26
am654_sdhci mmc@4f80000: Couldn't find ti,otap-del-sel-sd-hs
am654_sdhci mmc@4f80000: Couldn't find ti,otap-del-sel-sdr12
am654_sdhci mmc@4f80000: Couldn't find ti,otap-del-sel-sdr25
am654_sdhci mmc@4f80000: Couldn't find ti,otap-del-sel-sdr50
am654_sdhci mmc@4f80000: Couldn't find ti,otap-del-sel-ddr50
am654_sdhci mmc@4f80000: Couldn't find ti,otap-del-sel-sdr104
single-pinctrl pinctrl@11c000: 67 pins
single-pinctrl pinctrl@11c000: configuring pins for main-mmc1-default-pins
single-pinctrl pinctrl@11c000:   reg/val 0x000000000011c104/0x00050000
single-pinctrl pinctrl@11c000:   reg/val 0x000000000011c100/0x00050000
single-pinctrl pinctrl@11c000:   reg/val 0x000000000011c0fc/0x00050000
single-pinctrl pinctrl@11c000:   reg/val 0x000000000011c0f8/0x00050000
single-pinctrl pinctrl@11c000:   reg/val 0x000000000011c0f4/0x00050000
single-pinctrl pinctrl@11c000:   reg/val 0x000000000011c0f0/0x00050000
single-pinctrl pinctrl@11c000:   reg/val 0x000000000011c0ec/0x00050000
single-pinctrl pinctrl@11c000:   reg/val 0x000000000011c0e4/0x00050008
am654_sdhci mmc@4fb0000: Couldn't find ti,otap-del-sel-mmc-hs26
am654_sdhci mmc@4fb0000: Couldn't find ti,otap-del-sel-mmc-hs
am654_sdhci mmc@4fb0000: Couldn't find ti,otap-del-sel-ddr52
am654_sdhci mmc@4fb0000: Couldn't find ti,otap-del-sel-hs200
am654_sdhci mmc@4fb0000: Couldn't find ti,otap-del-sel-hs400
mmc@4f80000: 0, mmc@4fb0000: 1
Loading Environment from nowhere... OK
In:    serial@40a00000
Out:   serial@40a00000
Err:   serial@40a00000
single-pinctrl pinctrl@4301c068: configuring pins for mcu-cpsw-default-pins
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c068/0x00010000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c06c/0x00050000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c070/0x00010000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c074/0x00010000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c078/0x00010000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c07c/0x00010000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c088/0x00050000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c08c/0x00050000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c090/0x00050000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c094/0x00050000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c080/0x00010000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c084/0x00050000
single-pinctrl pinctrl@4301c068: configuring pins for mcu-mdio1-default-pins
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c09c/0x00010000
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c098/0x00050000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1
Net:   am65_cpsw_nuss_port ethernet@46000000port@1: old gmii_sel: 00000001
am65_cpsw_nuss_port ethernet@46000000port@1: gmii_sel PHY mode: 11, new gmii_sel: 00000002
eth0: ethernet@46000000port@1
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0(part 0) is current device
SD/MMC found on device 0
Can't set block device
** No partition table - mmc 0 **
single-pinctrl pinctrl@4301c068: configuring pins for wkup-gpio-default-pins
single-pinctrl pinctrl@4301c068:   reg/val 0x000000004301c0d8/0x00050007
single-pinctrl pinctrl@11c000: configuring pins for main-i2c0-default-pins
single-pinctrl pinctrl@11c000:   reg/val 0x000000000011c0d4/0x00060000
single-pinctrl pinctrl@11c000:   reg/val 0x000000000011c0d8/0x00060000
Timed out in wait_for_event: status=0000
Check if pads/pull-ups of bus are properly configured
Timed out in wait_for_event: status=0000
Check if pads/pull-ups of bus are properly configured
Timed out in wait_for_event: status=0000
Check if pads/pull-ups of bus are properly configured
Timed out in wait_for_event: status=0000
Check if pads/pull-ups of bus are properly configured

    Here we identified that it was trying to configure main-i2c0, but it didn’t detect the pull-up resistors, which makes sense, as our custom board doesn’t have them.

    To address this, we modified the Device Tree and disabled main-i2c along with some SerDes configuration.
    We still have a few issues, but with these changes we were at least able to reach the U-Boot console.

    Here’s the relevant Device Tree diff:

    diff --git a/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts b/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts
index 735ffd3f..5a814890 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts
+++ b/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts
@@ -18,13 +18,26 @@
 	model = "Texas Instruments J7200 EVM";
 
 	aliases {
-		serial0 = &wkup_uart0;
+		/* WKUP_UART CONFIG */
+		/* 
+		serial0 = &main_uart0;
 		serial1 = &mcu_uart0;
-		serial2 = &main_uart0;
+		serial2 = &wkup_uart0;
 		serial3 = &main_uart1;
 		serial5 = &main_uart3;
 		mmc0 = &main_sdhci0;
 		mmc1 = &main_sdhci1;
+		*/
+
+		/* MCU_UART CONFIG */
+		serial0 = &main_uart0;
+		serial1 = &wkup_uart0;
+		serial2 = &mcu_uart0;
+		serial3 = &main_uart1;
+		serial5 = &main_uart3;
+		mmc0 = &main_sdhci0;
+		mmc1 = &main_sdhci1;
+		
 	};
 
 	chosen {
@@ -270,7 +283,7 @@
 
 &wkup_uart0 {
 	/* Wakeup UART is used by System firmware */
-	status = "reserved";
+	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&wkup_uart0_pins_default>;
 	bootph-all;
@@ -345,7 +358,7 @@
 };
 
 &main_i2c0 {
-	status = "okay";
+	status = "disbaled";
 	pinctrl-names = "default";
 	pinctrl-0 = <&main_i2c0_pins_default>;
 	clock-frequency = <400000>;
@@ -448,31 +461,31 @@
 	clock-frequency = <100000000>;
 };
 
-&serdes0 {
-	serdes0_pcie_link: phy@0 {
-		reg = <0>;
-		cdns,num-lanes = <2>;
-		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_PCIE>;
-		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
-	};
-
-	serdes0_qsgmii_link: phy@1 {
-		reg = <2>;
-		cdns,num-lanes = <1>;
-		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_QSGMII>;
-		resets = <&serdes_wiz0 3>;
-	};
-};
-
-&pcie1_rc {
-	status = "okay";
-	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
-	phys = <&serdes0_pcie_link>;
-	phy-names = "pcie-phy";
-	num-lanes = <2>;
-};
+// &serdes0 {
+// 	serdes0_pcie_link: phy@0 {
+// 		reg = <0>;
+// 		cdns,num-lanes = <2>;
+// 		#phy-cells = <0>;
+// 		cdns,phy-type = <PHY_TYPE_PCIE>;
+// 		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+// 	};
+
+// 	serdes0_qsgmii_link: phy@1 {
+// 		reg = <2>;
+// 		cdns,num-lanes = <1>;
+// 		#phy-cells = <0>;
+// 		cdns,phy-type = <PHY_TYPE_QSGMII>;
+// 		resets = <&serdes_wiz0 3>;
+// 	};
+// };
+
+// &pcie1_rc {
+// 	status = "okay";
+// 	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+// 	phys = <&serdes0_pcie_link>;
+// 	phy-names = "pcie-phy";
+// 	num-lanes = <2>;
+// };
 
 &mcu_mcan0 {
 	status = "okay";
diff --git a/dts/upstream/src/arm64/ti/k3-j7200-main.dtsi b/dts/upstream/src/arm64/ti/k3-j7200-main.dtsi
index 8757bb7a..653dbf99 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j7200-main.dtsi
@@ -702,61 +702,61 @@
 		status = "disabled";
 	};
 
-	serdes_wiz0: wiz@5060000 {
-		compatible = "ti,j721e-wiz-10g";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
-		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
-		num-lanes = <4>;
-		#reset-cells = <1>;
-		ranges = <0x5060000 0x0 0x5060000 0x10000>;
-
-		assigned-clocks = <&k3_clks 292 85>;
-		assigned-clock-parents = <&k3_clks 292 89>;
-
-		wiz0_pll0_refclk: pll0-refclk {
-			clocks = <&k3_clks 292 85>, <&serdes_refclk>;
-			clock-output-names = "wiz0_pll0_refclk";
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz0_pll0_refclk>;
-			assigned-clock-parents = <&k3_clks 292 85>;
-		};
-
-		wiz0_pll1_refclk: pll1-refclk {
-			clocks = <&k3_clks 292 85>, <&serdes_refclk>;
-			clock-output-names = "wiz0_pll1_refclk";
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz0_pll1_refclk>;
-			assigned-clock-parents = <&k3_clks 292 85>;
-		};
-
-		wiz0_refclk_dig: refclk-dig {
-			clocks = <&k3_clks 292 85>, <&serdes_refclk>;
-			clock-output-names = "wiz0_refclk_dig";
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz0_refclk_dig>;
-			assigned-clock-parents = <&k3_clks 292 85>;
-		};
-
-		wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
-			clocks = <&wiz0_refclk_dig>;
-			#clock-cells = <0>;
-		};
-
-		serdes0: serdes@5060000 {
-			compatible = "ti,j721e-serdes-10g";
-			reg = <0x05060000 0x00010000>;
-			reg-names = "torrent_phy";
-			resets = <&serdes_wiz0 0>;
-			reset-names = "torrent_reset";
-			clocks = <&wiz0_pll0_refclk>;
-			clock-names = "refclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-	};
+	// serdes_wiz0: wiz@5060000 {
+	// 	compatible = "ti,j721e-wiz-10g";
+	// 	#address-cells = <1>;
+	// 	#size-cells = <1>;
+	// 	power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
+	// 	clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+	// 	num-lanes = <4>;
+	// 	#reset-cells = <1>;
+	// 	ranges = <0x5060000 0x0 0x5060000 0x10000>;
+
+	// 	assigned-clocks = <&k3_clks 292 85>;
+	// 	assigned-clock-parents = <&k3_clks 292 89>;
+
+	// 	wiz0_pll0_refclk: pll0-refclk {
+	// 		clocks = <&k3_clks 292 85>, <&serdes_refclk>;
+	// 		clock-output-names = "wiz0_pll0_refclk";
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz0_pll0_refclk>;
+	// 		assigned-clock-parents = <&k3_clks 292 85>;
+	// 	};
+
+	// 	wiz0_pll1_refclk: pll1-refclk {
+	// 		clocks = <&k3_clks 292 85>, <&serdes_refclk>;
+	// 		clock-output-names = "wiz0_pll1_refclk";
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz0_pll1_refclk>;
+	// 		assigned-clock-parents = <&k3_clks 292 85>;
+	// 	};
+
+	// 	wiz0_refclk_dig: refclk-dig {
+	// 		clocks = <&k3_clks 292 85>, <&serdes_refclk>;
+	// 		clock-output-names = "wiz0_refclk_dig";
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz0_refclk_dig>;
+	// 		assigned-clock-parents = <&k3_clks 292 85>;
+	// 	};
+
+	// 	wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
+	// 		clocks = <&wiz0_refclk_dig>;
+	// 		#clock-cells = <0>;
+	// 	};
+
+	// 	serdes0: serdes@5060000 {
+	// 		compatible = "ti,j721e-serdes-10g";
+	// 		reg = <0x05060000 0x00010000>;
+	// 		reg-names = "torrent_phy";
+	// 		resets = <&serdes_wiz0 0>;
+	// 		reset-names = "torrent_reset";
+	// 		clocks = <&wiz0_pll0_refclk>;
+	// 		clock-names = "refclk";
+	// 		#address-cells = <1>;
+	// 		#size-cells = <0>;
+	// 	};
+	// };
 
 	pcie1_rc: pcie@2910000 {
 		compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
diff --git a/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
index d9a40b48..bb5f937c 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
@@ -274,7 +274,7 @@
 		compatible = "ti,j721e-uart", "ti,am654-uart";
 		reg = <0x00 0x42300000 0x00 0x100>;
 		interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
+		clock-frequency = <96000000>;
 		power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 287 2>;
 		clock-names = "fclk";

    I don’t have a saved log of the working U-Boot console yet, but I’ll include it later.

    We also noticed that the board resets after some time while we are testing commands in the U-Boot terminal.
    Could this be related to the timeout for the UART boot mode?
    Or could it be caused by a timeout configuration in some device from the Device Tree?
    Do you have any idea what could be causing this issue?

    Thanks again for your help!

    Best regards,
    Santi

  • 0 in reply to Santiago Pérez
    TI__Guru**** 170530 points

    Santi,

    Is there a crash followed by reset? If not then it could be some watchdog timeout. I am unsure if you have configured PMIC watchdog.

    Best Regards,

    Keerthy 

  • 0 in reply to Keerthy J
    Prodigy 160 points

    Hi Kerthy,

    Thanks for the quick reply!
    We didn’t observe any crash messages before the reset, the board simply resets after some time (around 6 minutes - we just measure this time once) while we are testing commands in the U-Boot console. When the board reset we see again the stings of the uart boot mode:

    00CC01000000011a00006a3776636c00000000000000475020200000020000000200CC

    We haven’t explicitly configured the PMIC watchdog, is not configured by default for the TI SDK?.

    Best regards,
    Santiag

  • 0 in reply to Santiago Pérez
    TI__Guru**** 170530 points
    Santiago Pérez said:

    We haven’t explicitly configured the PMIC watchdog, is not configured by default for the TI SDK?.

    Depends on the Board & dip switch settings. SOC RTI watchdogs not enabled by default.

    Is there a different boot mode that you can try now?

    OSPI or eMMC?

    https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-j722s/11_01_00_03/exports/docs/linux/Foundational_Components/U-Boot/UG-QSPI.html

    This will help you debug faster as UART boot is super slow!

    - Keerthy

  • 0 in reply to Keerthy J
    Prodigy 160 points

    Hi Kerthy,

    We have eMMC available, but I’m not sure if OSPI is present on our custom board, I’ll check and confirm with our HW team. That was actually our next step: we’re planning to flash the eMMC, but at the moment we can only flash through UART, and we haven’t tested this boot flow yet on the EVM.

    We’ve been reviewing this document:
    https://www.ti.com/lit/an/spracy5/spracy5.pdf

    We believe that using UniFlash will be the best option for flashing the eMMC boot0 partition. By the way, if you have any better suggestions, we’re open to your recommendations.

    Regarding this point:

    Keerthy J said:
    Depends on the Board & dip switch settings. SOC RTI watchdogs not enabled by default.

    I’m not sure if we’ve taken these DIP switches into account. To be honest, I’m not completely sure which DIP switches you’re referring to are these the ones located on the SOM? I couldn’t find specific information about them.

    Best regard,

    Santi

  • 0 in reply to Santiago Pérez
    TI__Guru**** 170530 points

    Hello Santi,

    Once you boot to U-Boot prompt then you can use U-Boot itself to burn the binaries to either eMMC or ospi.

    The documentation like that i shared above shows the steps to flash the binaries to eMMC.

    Dip switches to change the boot modes is on the common processor board of the EVM.

    Best Regards,

    Keerthy 

  • 0 in reply to Keerthy J
    Prodigy 160 points

    Hi Kerthy,

    Yes, we have tested loading the files directly through U-Boot on the EVM. We also tried using Uniflash, but we couldn’t get that tool to work properly.

    I think we can close this thread, as we’ve moved quite far beyond the original topic.

    For any further issues, I’ll open a new thread. We still need to test your suggestion regarding the PMIC switch configuration on our custom board.

    Thanks a lot for your support and help!

    Hope to see you again in future posts :)

    Best regards,

    Santi