Tool/software:
Per AM64x PCB Guideline, the LP4_DRS5, DQ/DM to DQS skew is required with maximum 150psec.
Could you clarify the max 150psec means that DQ/DM to DQS skew is +/-75ps which means that DATA byte can be either 75ps shorter (approximately -450mils) or 75psec longer (approximately +50mils) than DQS ?
