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AM335x with DDR3 - routing guidelines and device speed questions

Stephanie Goedecke
Prodigy 165 points

The DDR3 routing guidelines section in the AM335x datasheet are different from what I expected. They say for 2 x8 DDR3 devices, only dual-side mounting is supported, and the address and control signals must use parallel termination, instead of serial termination which is normally recommended with so few DDR3 devices.  They also say devices must support at least 800 MHz.  But the DDR3 clock will run at 303 MHz, so a 606 MHz data rate. 

Does TI have simulations that show 667 MHz DDR3 devices are too slow or will not work with this memory controller? 

Also, are there simulations that show serial termination will not work?  I have a reference schematic from TI called Frost Byte which has DDR3 SDRAM with serial termination.  Has that board been built?  If it has, does its DDR3 interface work?

thanks 

 

  • 0
    Intellectual 290 points

    Hi Stephanie, I've been looking at this, too.

    In the latest datasheet (sprs717b) Table 5-50 Supported DDR3 Device Combinations in section 5.4.2.3 shows 2 devices, mirrored:Y . It is initially not clear whether "supported" here means "allowed" or "mandated."On further reading, I understand that a mirrored configuration is not compulsory and that having both devices on a single side is allowed.

    Section 5.4.2.3.3.4 Placement says "The placement does not restrict the side of the PCB on which the devices are mounted"

    Section 5.4.2.3.4.1 Two DDR3 devices says:

    "Two DDR3 devices are supported on the DDR3 interface consisting of two x8 DDR3 devices arranged as one 16-bit bank. These two devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at a cost of increased routing complexity and parts on the backside of the PCB"

    Also note(5) under table 5-59 says: "Non-mirrored configuration (all DDR3 memories on same side of PCB)

    This is unambiguous.

    It would be helpful if Table 5-50 had initially been clearer.

    The lowest speed grade of DDR3 described by JEDEC is DDR3-800(I  believe DDR3-667 does not exist) This usually runs with a 400MHz clock as noted in note(1) under Table 5-51. (This serves to confuse the reader)

    However,

    Table 3-5 Operating points for the ZCZ Package shows the DDR3 clock running at just 303MHz.

    Note (4) below the table explains: The JEDEC JESD79-3E specification defines the maximum clock period of 3.3ns for all standard-speed bin DDR3 memory devices. Therefore, all standard-speed bin DDR3 memory devices are required to operate at 303MHz.

    Table 5-49 shows that the AM335x can operate the DDR3 memory clock at a maximum of 303MHz, which is also the minimum required frequency for DDR3 devices. The lowest speed grade device that will support this is DDR3-800.

    DDR2 devices were usually wired in a balanced T-arrangement. DDR3 devices are wired in a daisy-chain fly-by topology. This minimises stub lengths for improved signal integrity but causes issues with clock skew. To compensate for this DDR3 provides a write-levelling feature which allows the controller to compensate for clock skew differences.

    It may be that this topology and the way the on-device terminators(ODT) work means that source series termination won't work.

    Note(13) under table 5-59 states: "Source termination (series resistor at driver) is specifically not allowed.

    This is with reference to termination for the CK and ADDR_CTRL nets, which use end of line termination.

    The DQ and DQS signals use built-in ODT . Table 5-60, note(2) says: "External termination disallowed. Data termination should use built-in ODT functionality."

    I hope this helps

    Regards

    Roger.