AM5708: DDR3 Impedance Settings

Part Number: AM5708

Tool/software:

I am configuring a system using DDR3.

To match the DDR3 impedance, I need to set the impedance of the single-ended and differential signals.

According to the AM5708 manual, I can set Imp80 to Imp34Ω by setting "l[2:0] =".

I'm not sure if this setting is common to both single-ended and differential signals, or if it can be set separately.

My understanding is that setting "l[2:0] = 010(Imp48)" will result in an output impedance of Imp48Ω for both single-ended and differential signals.

Or, for example, if I set it to Imp48 (48Ω), is it correct to understand that the single-ended impedance is 48Ω and the differential signal impedance is 96Ω?

I'm in a hurry, so a quick response would be appreciated.

Thank you in advance.

Hiroshi Yamada

  • Hi,

    I'm not sure if this setting is common to both single-ended and differential signals, or if it can be set separately.

    There are separate output impedance control settings for the DDR DQ (single-ended) signals and the DDR DQS (differential) signals. 

    Table 18-25 (of section 18.4.6.10 "Software Controls for the DDR3 I/O Cells") in the TRM (revised April 2024) documents the register mapping of the output impedance control signals to specific DDR pads. 

    https://www.ti.com/lit/pdf/spruhz7 

    Regards,
    Kevin