• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 97 subscribers
  • Views 460 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6748: uHPI vs uPP interface between FPGA and DSP

PR
Prodigy 50 points

Part Number: TMS320C6748

Tool/software:

Hello,

Need to interface ADC => FPGA <=> DSP, ADC data is sampled by FPGA and sent to DSP for FIR filter implementation.

This filtered data from DSP is readback by FPGA. 

ADC Data: 200MSPS 

DSP clock: 456MHz 

Which interface is more feasible in terms bandwidth (200MSPS ADC data) and bidirectional communication.

Regards 

  • 0
    TI__Intellectual 1440 points

    Hello Riki,

    To check bandwidth and pick the right interface, could you please share:

    • Bits per sample and number of channels or streams.
    • Is the 200 MSPS continuous?
    • Do you need simultaneous FPGA->DSP and DSP->FPGA? If so, what's the return rate?

    With these parameters, I can give you a better answer for your system.

    Regards,
    Karam

  • 0 in reply to Karam Haddad
    Prodigy 50 points

    Hello Karam,

    Between ADC and FPGA, max rate is 200MSPS continuous (Configurable to lower values, but this is the worst case). FPGA would put some windowing method and decimate the data to eg Divide by 8, so around 25MSPS (Max).

    1 ADC sample is 12bits.

    For communication: 

    1) A full Duplex FPGA/ DSP would give more flexibility, but I believe uHPI has limitation and uPP can achieve this by using both A and B channels

    2) A half Duplex FPGA/ DSP would be second option.

    I would request feasibility with both uHPI/ uPP for above with limitations/ advantages of each.

    Regards     

  • 0 in reply to PR
    TI__Intellectual 1440 points

    Hello Riki,

    Given the specifications you have provided, I recommend using uPP. It's purpose-built for high-speed streaming to FPGA/data converters, supports full-duplex mode with the A/B channels, and provides a clocked interface, making it ideal for continuous data.

    UHPI only works in half-duplex mode, is asynchronous with no streaming clock, and transfers are host-driven making it not ideal for continuous data streams. UHPI also typically requires more software and setup compared to uPP.

    Regards,
    Karam

  • 0 in reply to Karam Haddad
    Prodigy 50 points

    Hello Karam, 

    1. For uPP, using only 1 channel (Either Channel A or Channel B) is it possible to have half duplex communication on the fly (without Rest/ configuration change)? 

    2A. If re-configuration (as per section 31.2.6.1) is needed for Transmit to Receive change, then how much time it takes for 456Mhz sysclk (200* 1/456M)  = ~ 0.5us?

    2B. If uPP needs to be rest for changing the T/R direction does it affect the internal RAM contents?   

    3. Also, for 10bits ADC, can we connect Channel A (10 signal line only) and Channel B (10 Signal lines only)? Kindly confirm the row/ option as per below table

      

    4. In Full Duplex mode, if using 10bits ADC then the channel A [9:0] will be as per last row of the above table. Keeping the other lines open/ Not-connect.  

    Regards

  • 0 in reply to PR
    TI__Intellectual 1440 points

    Hi Riki, 

    Please allow me some time to look at this and I will get back to you Monday with an update.

    Regards,
    Karam

  • 0 in reply to PR
    TI__Intellectual 1440 points

    Hello Riki,

    1) Each channel of uPP must be configured as TX or RX via UPCTL. Half duplex cannot be done on the fly since it requires changing the uPP mode and registers. Check Table 31-7 Basic Operating Mode Selection of the TMS320C6748 DSP TRM.

    2A) As described in Section 31.2.6.1 Step-by-Step Procedure of TMS320C6748 DSP TRM, Step 4 mentions to wait at least 200 device clock cycles, so clearing does take about 0.5 us.

    2B) The SWRST register clears internal state machines and DMA logic, it does not affect device or DSP memory. Register description can be found in TMS320C6748 DSP TRM Table 31-12 uPP Peripheral Control Register (UPPCR) Field Descriptions

    3) uPP supports 8-16 bits so you can connect each channel to 10 bits by configuring the iWx bit in UPCTL. The extra bits are filled by uPP according to the data packing scheme selected by the DFWx bit in UPCTL. Refer to TMS320C6748 DSP TRM 31.2.5.8 Data Format section for more information.

    4) Unused bits can be NC as long as the uPP is configured as described in point 3 of this response.

    Regards,
    Karam