Part Number: AM67A
Other Parts Discussed in Thread: BEAGLEY-AI
Tool/software:
Hi,
My customer is asking us about LPDDR4 configuration.
Could you confirm following questions and send me your feedback ?
Premise :
* Customer is refering following two information.
1. Jacinto7 AM6x/TDA4x/DRA8x LPDDR4 Design Guidelines
https://www.ti.com/jp/lit/an/spracn9f/spracn9f.pdf
2. Layout of BEAGLEY-AI board
https://www.beagleboard.org/boards/beagley-ai
Q1. According to design guideline application note (Above "1"), there is layout example on "Table 3-4. Example PCB Stackup for LPDDR4".
This stackup example show that "DBG"(Data Byte Group) is assigned "L2".
On the other hand, layout of beagleY(above "2") show that "DBG"(Data Byte Group) is assigned "L3".
Customer would like to apply layout same as beagleY. However, is there any concern when user apply layout that "DBG"(Data Byte Group) is assigned "L3" ?
Q2. According to design guideline application note (Above "1"), It seems that TI recommend to use low permittivity material than general "FR-4" depending on DDR speed and layout configuration.
In following case, which material general "FR-4" or low permittivity is better to be used ?
- 10 layer with backdrill
- DDR speed grade is 3733Mbps
If you have any other guideline to determine material, could you please let me know ?
(In general, I think user perform kind of RF measurement simulation, however this need additional cost, so if you have any standard guideline we would like to know that.)
Best Regards,