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OMAP ISP camera sync pulses requirement

Aditya Pogade55079
Prodigy 185 points
Other Parts Discussed in Thread: OMAP3530

Hi,

My colleague has already posted query regarding 512 x 512 camera capture issue. To brief you all about the problem is we are designing a camera hardware board that will generate all sync pulses and clocks for CCDC of OMAP3530. Currently we are generating all these pulses using counters and gate logic and fed it to OMAP3530 camera interface. 

HSYNC pulse = Pulse HIGH for 504 pixel clock + Pulse LOW for 8 pixel clocks.

VSYNC pulse = Pulse HIGH for 504 HSYNC + Pulse LOW for 8 HSYNC.

However we are unable to capture 504 lines; instead I capture only 490 lines. Please note that we have 4 MHz as pixel clock. 

I understand there is relation between pixel clock, sync signals and frame rate. But don't know what? Can anybody please provide me more details of sync signals generation. 

What would be the timing details of sync signal for VSYNC?

What would be the duration between two VSYNC pulses?

Is there any specific requirement of ISP for sync pulses?

Relation of pixel clock, sync pulses and frame rate?

I would be grateful, if anybody could answer my any of above questions.

Thanks & regards,

Aditya

  • 0
    Prodigy 185 points

    One more point I would like to add about my observations is - 

    Time duration between two VSYNC pulses = Number of lines + Delay.

    I would like to understand what is this delay.

    I would appreciate if someone could help me in this. 

    Thanks & regards,

    Aditya

  • 0 in reply to Aditya Pogade55079
    Prodigy 30 points

    Hi Aditya,

    1. The delay is the Vertical blanking interval. One example where it is used, This is what that is used to superimpose text in the  screen while the display is running.

    2. The OMAP3530 receives a byte every pixel clock. For eg. for every clock the D0 to D7 bits are sampled and a byte data is read.Pixel clock is thus used for sampling data. For eg. if you need 640*480 at 30fps then, at 16 bits per pixel(2 pixel clocks for 16 bits), you would need a minimum pixel clock rate of 640*480*30*2 = 18.432 Mhz.

    3. The number of VSYNCs per second is the frame rate.

    Lakshmi

  • 0 in reply to Lakshmi Narsimhan88741
    Prodigy 185 points

    Thanks Lakhsmi for your reply!!

    This matches my understanding; however was not getting any justification document. Thanks a lot!!

    One more question - is there way we can reduce vertical blanking to zero, assuming that we don't have to connect a display to the platform or to superimpose any text in the acreen. If yes, what control register do we need to tweek with to make this happen.

    Once again, I appreciate your reply.

    Thanks & regards,

    Aditya