32bit DDR3 interface Vs 16bit DDR3 interface performance

Yes, switching to 16 bit will half the available bandwidth.

Theoretical bandwidth is simply clock speed x bus width x 2

For a clock speed if 400MHz and 32 bit width you get 400 x 32 x 2 MBits/second = 25600 MBits/sec or 3200MBytes/s

This is the theoretical max. In reality it depends very much on your application's usage of memory but a good estimate is about 65% of this max is what you will realistically be able to achieve.

BR,

Steve

Dear Steve-san,

I apologize for my interrupt.

I have similar question for DDR3 performance.

In theoretical bandwidth calculation you commented, is this formula applied for 64bit bus?

I would like to know how fast bas width from 32bit to 64bit for DDR3 access.

Please let me know.

Best regards,

Michi

Michi,

If you notice in the explanation there is a multiplication by 32 for a 32 bit wide bus.

The 81xx does not directly support a 64 bit bus, but it does support dual 32 bit buses, so you can still use the calculation by multiplying by 2 (same results for either dual 32 bit or single 64 bit theoretical)

BR,

Steve

Steve-san,

Thank you for your reply. I understood it.

By the way, I have one more question regarding DDR3.

DM814x/AM387x does not have the error detection for DDR3 memory like ECC, parity check and so on.

How does customer implement the error detection to their system?

If you have some idea, please let me know.

Best regards,

Michi

I don't believe there are any automatic or real time ways to do this without actually using ECC memory.

You could periodically checksum memory if you know it should not change, but beyond this I don't think there is much else you can do.

BR,

Steve

Steve-san,

Thank you for your reply.

Please give me more information for "checksum memory" you said.  Do you mean the special memory for storing checksum is used?

Our customer has never experienced to use DDR3 memory. And they think DDR3 is difficult to use for high speed and low voltage.

So they believe that some memory error detection should be implemented to their AM3874 system. How do you think about their thought?

Please advise me.

Best regards,

Michi

By "checksum memory" I mean you can read the memory region and calculate a checksum in software, then periodically re-read the memory and re-calculate the checksum to see if anything has changed. If things changed unexpectedly then something is corrupt. This requires your software to do this process though. It is not automatic nor real time and can only be used on memory that does not actually change.

DDR3 is not really more difficult than DDR2 or regular DDR.

If their system is generating errors then it is a bad PCB design.

Error correcting memory is only necessary in systems which are life critical and need to be prepared for actual memory device failure or to protect against cosmic radiation.

The memory should never become corrupt during 'normal' operation.

If they want to implement error correction because they are not comfortable designing DDR3 systems then I recommend they sub-contract the board design to someone who has experience with DDR3.

BR,

Steve

Dear Steve-san,

Thank you for your forceful comment.

By the way, I would like to know one thing. As you know, AM3874's DDR2/3/mDDDR Memory Controller has "Write/Read Leveling" feature for DDR3 memory.

Is this feature supported by AM387x_WEC7 BSP? I think this feature helps to protect happening the memory error when read/writing. If BSP will support this

feature, customer can use this feature, can't it?

Best regards,

Michi 

Hi ,

Write levelling feature is part of DDR3. The Read/write levelling goal is to compensate all the skews and specifically the skew between DQSx and DDR CLK . This is part of a DDR3 unit which is called DTU, (Data Unit Training). This is a block inside DDR and customer do not have access to this. All DTU trainings operations are done at DDR power ON. Customer's application do not has to deal with.

Hope it's clear.

B.R.

Nasser