TDA4VL-Q1: Minimum CSI2Rx line width

Jin Lee

Part Number: TDA4VL-Q1

Hi,

What is the minimum line width supported by CSI2Rx? We are using the the driver from J721S Linux SDK for a custom TDA4VL-Q1 board.

Thank you,

Jin

3 months ago

0 Robert Eschler 3 months ago

TI__Guru 54165 points

The CSI2-RX is a MIPI D-PHY interface meaning its impedance requirements are 100-ohm differential (loosely) and 50-ohm single-ended. The required trace width for that impedance is driven by the PCB stack-up and PCB manufacturer. Minimum trace width is controlled by the PCB manufacturer.

0 Jin Lee 3 months ago in reply to Robert Eschler

TI__Expert 3547 points

Hi Robert,

Sorry for confusion I meant in the context of the CSI2 frame - i.e. the minimum number of bytes per line.

+1 Mark L. 3 months ago

TI__Expert 5820 points

Hi Jin,

Per MIPI D-PHY v2.1 spec, minimum number of bytes per line is 1

Regards,
Mark

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TDA4VL-Q1: Minimum CSI2Rx line width