TDA4VM: Interrupt Router register access

Hi,

To be more specific, i am developing diagnostics for the NAVSS Interrupt Router. I understand that TISCI manages resource allocation and access control for this module.

But for implementing diagnostics, i would like to understand the following:

1. Is it possible or supported to directly access the NAVSS interrupt router registers (e.g., at 0x310E0000) from the application processor, bypassing TISCI?
2. Are these registers firewalled or restricted to DMSC firmware access only?
3. From a functional safety perspective, would direct register access be discouraged even if technically possible?
4. If direct access is blocked, is there a TISCI message or query API that allows retrieving the current routing configuration for verification purposes?

Hello,

Adithya G B said:

For Interrupt Router configuration, is it possible to access the router registers( eg: for reading the interrupt enable bit) directly without using Tisci client APIs?

To do interrupt routing you definitely need SCICLIENT API and DM has to serve this SCICLIENT request.  

Direct manipulation of interrupt routing registers are not advisable, the whole system might break since DM will fail to know which core is using which interrupt.

Regards

Tarun MUkesh

Hi Tarun,

Thanks for the feedback and I understand your point. 

I am checking with you, if register access is possible from the kernel level, for performing some diagnostic tests. Like for eg: reading back the register. In these scenarios we will not be modifying the register but just checking the values. In such a case, is it possible to access the router registers without using SCICLIENT API?

I have a follow-up question as well. If we can only proceed using SCICLIENT APi's, is there any way to retrieve the router register configuration through SCI? 

Kindly get back to me as soon as possible. Appreciate the quick response.

Thankyou!

Hello,

Adithya G B said:

I have a follow-up question as well. If we can only proceed using SCICLIENT APi's, is there any way to retrieve the router register configuration through SCI? 

what exactly you want to do with reading back router register configuration from kernel level ? what kind of diagnostic tests on interrupt routers ?

Even if you read router registers it will not be clear , how are you planning to read it ?

Regards

Tarun Mukesh

Hi Tarun,

We are planning to implement the following diagnostics mentioned in TI's safety manual (SFFS462_J784S4_TDA4AP_TDA4VP_TDA4AH_TDA4VH_SafetyManual_v0.99.pdf):

e2e.ti.com/.../5315.SPRUJ52-_2D00_-J84S4-AM69A-TRM.pdf

• INTR1 - Software Read Back of Written Configuration
• INTR2 - Periodic Software Read Back of Static Configuration Registers
• INTR3 - Software Test of Basic Functionality

For implementing these diagnostics, we need access to register configuration. Which is why I am asking if there is any way to access the router configuration through SCI client?

Also, is DM reading back the register confirming the configuration before sending the Acknowledgement to the TISCI?

In this scenario, would it be okay to just validate the acknowledgement from the SCI client to ensure safety?

Hello Adithya,

Adithya G B said:

Which is why I am asking if there is any way to access the router configuration through SCI client?

My understanding is only DM core can access these registers but not any other cores .

May be you can try reading the registers what you want to do readback then if exception comes it is protected else you could read 

Adithya G B said:

DM reading back the register confirming the configuration before sending the Acknowledgement to the TISCI?

Hi Tarun,

Thanks for valuable and quick response. I have understood your points.

I have one more doubt regarding this : For doing basic functionality test for the Interrupt Router without accessing the register how can i verify the functionality? Can i use the acknowledgement message from the SCICLIENT to confirm that a successful routing has been done?

Regards,

Adithya G B