J784S4XEVM: Graph Verify Failed when running a model with Gridsample

Hi Ghassen, 

When running inference on PC emulation, do these two models both run?

Warm regards,

Christina

Hello Christina,

Thank you for your reply.

I tried another model with add node after the gridsample node and I have these results:

On PC: inference is running

On board: I have this error 

Here is the model: 8738.gridsample_model.zip

Can you please help me with this model?

Hi Ghassen, 

For this model you just shared, could you also share the model configuration and input you use, as well as any other changes?

I will see if I can recreate the behavior on my side. Which version of edgeai-tidl-tools are you using?

Warm regards,

Christina

Hello Christina,

I'm using edgeai-tidl-tools version 10_00_06_00.

Here is the configuration used during the compilation.

"gridsample_model" : 
    {
        "cpu_provider_options"  :   {}, 
        "tidl_provider_options" :   {
                                     "tidl_tools_path"                           : os.path.join(ROOT_DIR, "edgeai-tidl-tools", "tools", SOC, "tidl_tools"),
                                     "artifacts_folder"                          : MODELS_ARTIFACTS_BASE_PATH,
                                     "accuracy_level"                            : 1,
                                     "debug_level"                               : 4,
                                     "tensor_bits"                               : 16,
                                     "advanced_options:calibration_frames"       : 1,
                                     "advanced_options:calibration_iterations"   : 1,
                                     "allow_list:layer_name" : ""
                                },
        "output_names"           : [
                                    "y",
                                ],
        "session_options"       : {
                                      # Disable graph optimization to resolve graph optimization related errors when TIDL EP is used
                                      "graph_optimization_level"  : rt.GraphOptimizationLevel.ORT_DISABLE_ALL,
                                      "intra_op_num_threads"      : 1,
                                      "enable_profiling"          : False
                                }
    }

Here is the used inputs:

gridsample_model_dummy_data = {
    "x"             :   np.ones([1, 4, 28, 16], dtype = np.float32),
    "grid"          :   np.resize(arr, (1, 28, 16, 2))
}

And here is the model compilation log:

root@04543ce51ffc:/home/root# python3 scripts/run_model.py -m gridsample_model.onnx -c
ep_list: ['TIDLCompilationProvider', 'CPUExecutionProvider']
ep_options: [{'tidl_tools_path': '/home/root/scripts/../edgeai-tidl-tools/tools/AM69A/tidl_tools', 'artifacts_folder': '/home/root/scripts/../models_artifacts/gridsample_model_artifacts', 'accuracy_level': 1, 'debug_level': 4, 'tensor_bits': 16, 'advanced_options:calibration_frames': 1, 'advanced_options:calibration_iterations': 1, 'allow_list:layer_name': ''}, {}]
tidl_tools_path                                 = /home/root/scripts/../edgeai-tidl-tools/tools/AM69A/tidl_tools 
artifacts_folder                                = /home/root/scripts/../models_artifacts/gridsample_model_artifacts 
tidl_tensor_bits                                = 16 
debug_level                                     = 4 
num_tidl_subgraphs                              = 16 
num_tidl_subgraph_max_node                      = 0 
enable_rt_multi_subgraph_support                = 0 
tidl_denylist                                   = 
tidl_denylist_layer_name                        = 
tidl_denylist_layer_type                        = 
tidl_allowlist_layer_name                       = 
model_type                                      =  
tidl_calibration_accuracy_level                 = 7 
tidl_calibration_options:num_frames_calibration = 1 
tidl_calibration_options:bias_calibration_iterations = 1 
mixed_precision_factor = -1.000000 
model_group_id = 0 
power_of_2_quantization                         = 2 
ONNX QDQ Enabled                                = 0 
enable_high_resolution_optimization             = 0 
pre_batchnorm_fold                              = 1 
add_data_convert_ops                            = 0 
output_feature_16bit_names_list                 =  
m_params_16bit_names_list                       =  
m_single_core_layers_names_list                 =  
Inference mode                                  = 0 
Number of cores                                 = 1 
reserved_compile_constraints_flag               = 1601 
partial_init_during_compile                     = 0 
packetize_mode                                  = 0 
ti_internal_reserved_1                          = 

========================= [Model Compilation Started] =========================

Model compilation will perform the following stages:
1. Parsing
2. Graph Optimization
3. Quantization & Calibration
4. Memory Planning

============================== [Version Summary] ==============================

-------------------------------------------------------------------------------
|          TIDL Tools Version          |              10_01_00_01             |
-------------------------------------------------------------------------------
|         C7x Firmware Version         |              10_01_00_01             |
-------------------------------------------------------------------------------
|            Runtime Version           |                1.15.0                |
-------------------------------------------------------------------------------
|          Model Opset Version         |                  16                  |
-------------------------------------------------------------------------------

NOTE: The runtime version here specifies ONNXRT_VERSION+TIDL_VERSION
Ex: 1.14.0+1000XXXX -> ONNXRT 1.14.0 and a TIDL_VERSION 10.00.XX.XX

============================== [Parsing Started] ==============================

[TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options
[TIDL Import] [PARSER] SUPPORTED: Layers type supported by TIDL --- layer type - GridSample,  Node name -  -- [tidl_onnxRtImport_core.cpp, 600]
[TIDL Import] [PARSER] SUPPORTED: Layers type supported by TIDL --- layer type - Add,  Node name - Add_Ten -- [tidl_onnxRtImport_core.cpp, 600]

------------------------- Subgraph Information Summary -------------------------
-------------------------------------------------------------------------------
|          Core           |      No. of Nodes       |   Number of Subgraphs   |
-------------------------------------------------------------------------------
| C7x                     |                       2 |                       1 |
| CPU                     |                       0 |                       x |
-------------------------------------------------------------------------------
Running Runtimes GraphViz - /home/root/scripts/../edgeai-tidl-tools/tools/AM69A/tidl_tools/tidl_graphVisualiser_runtimes.out /home/root/scripts/../models_artifacts/gridsample_model_artifacts/allowedNode.txt /home/root/scripts/../models_artifacts/gridsample_model_artifacts/tempDir/graphvizInfo.txt /home/root/scripts/../models_artifacts/gridsample_model_artifacts/tempDir/runtimes_visualization.svg 
============================= [Parsing Completed] =============================

TIDL_createStateImportFunc Started:
Compute on node : TIDLExecutionProvider_TIDL_0_0
  0,      GridSample, 2, 1, x, gs_out
  1,             Add, 2, 1, gs_out, y

Input tensor name -  x 

Input tensor name -  grid 
Output tensor name - y 
In TIDL_onnxRtImportInit subgraph_name=subgraph_0
Layer 0, subgraph id subgraph_0, name=y
Layer 1, subgraph id subgraph_0, name=x
Layer 2, subgraph id subgraph_0, name=grid
==================== [Optimization for subgraph_0 Started] ====================
----------------------------- Optimization Summary -----------------------------
-------------------------------------------------------------------------------
|         Layer        | Nodes before optimization | Nodes after optimization |
-------------------------------------------------------------------------------
| TIDL_ConstDataLayer  |                         0 |                        1 |
| TIDL_EltWiseLayer    |                         1 |                        1 |
| TIDL_GridSampleLayer |                         1 |                        1 |
-------------------------------------------------------------------------------

=================== [Optimization for subgraph_0 Completed] ===================

In TIDL_runtimesPostProcessNet 
************ in TIDL_subgraphRtCreate ************ 
 The soft limit is 10240
The hard limit is 10240
MEM: Init ... !!!
MEM: Init ... Done !!!
 0.0s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO
 0.18s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR
 0.24s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING
 0.212s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel vx_tutorial_graph.phase_rgb on target DSP_C7-2
 0.231s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_sink on target MCU2-0
 0.240s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_source on target MCU2-0
 0.250s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_sink2 on target MCU2-0
 0.261s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_source2 on target MCU2-0
 0.270s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_intermediate on target MCU2-0
 0.279s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_intermediate_2 on target MCU2-0
 0.288s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_source_error on target MCU2-0
 0.297s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_source_obj_array on target MCU2-0
 0.307s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_sink_obj_array on target MCU2-0
 0.316s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_intermediate on target MCU2-0
 0.325s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_source on target MCU2-0
 0.334s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_sink on target MCU2-0
 0.342s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.test_target on target MCU2-0
 0.348s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.image_intermediate on target MCU2-0
 0.356s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.cmd_timeout_test on target MCU2-0
 0.362s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.tiovx_overhead on target MCU2-0
 0.368s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_sink on target MCU2-1
 0.374s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_source on target MCU2-1
 0.383s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_sink2 on target MCU2-1
 0.395s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_source2 on target MCU2-1
 0.403s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_intermediate on target MCU2-1
 0.412s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_intermediate_2 on target MCU2-1
 0.421s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_source_error on target MCU2-1
 0.429s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_source_obj_array on target MCU2-1
 0.437s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_sink_obj_array on target MCU2-1
 0.445s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_intermediate on target MCU2-1
 0.454s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_source on target MCU2-1
 0.463s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_sink on target MCU2-1
 0.471s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.test_target on target MCU2-1
 0.479s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.image_intermediate on target MCU2-1
 0.488s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.cmd_timeout_test on target MCU2-1
 0.496s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.tiovx_overhead on target MCU2-1
 0.507s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_sink on target MPU-0
 0.517s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_source on target MPU-0
 0.700s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_sink2 on target MPU-0
 0.715s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_source2 on target MPU-0
 0.725s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_intermediate on target MPU-0
 0.743s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_intermediate_2 on target MPU-0
 0.756s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_source_error on target MPU-0
 0.765s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_source_obj_array on target MPU-0
 0.945s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_sink_obj_array on target MPU-0
 0.955s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_intermediate on target MPU-0
 0.962s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_source on target MPU-0
 0.968s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_sink on target MPU-0
 0.974s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.test_target on target MPU-0
 0.980s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.image_intermediate on target MPU-0
 0.987s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.cmd_timeout_test on target MPU-0
 0.996s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.tiovx_overhead on target MPU-0
 0.1007s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.not_not on target MPU-1
 0.1016s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.not_not on target MPU-2
 0.1024s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.not_not on target MPU-3
 0.1030s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_sink on target DSP_C7-2
 0.1036s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_source on target DSP_C7-2
 0.1042s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_sink2 on target DSP_C7-2
 0.1048s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_source2 on target DSP_C7-2
 0.1067s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_intermediate on target DSP_C7-2
 0.1075s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_intermediate_2 on target DSP_C7-2
 0.1081s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_source_error on target DSP_C7-2
 0.1088s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_source_obj_array on target DSP_C7-2
 0.1093s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_sink_obj_array on target DSP_C7-2
 0.1099s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_intermediate on target DSP_C7-2
 0.1105s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_source on target DSP_C7-2
 0.1111s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_sink on target DSP_C7-2
 0.1117s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.test_target on target DSP_C7-2
 0.1123s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.image_intermediate on target DSP_C7-2
 0.1135s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.test_target on target DSP_C7-2
 0.1141s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.tiovx_overhead on target DSP_C7-2
 0.10235s:  VX_ZONE_INFO: [tivxInit:196] Initialization Done !!!
 0.10291s:  VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO
************ TIDL_subgraphRtCreate done ************ 
 ============= [Quantization & Calibration for subgraph_0 Started] =============
*******   In TIDL_subgraphRtInvoke  ******** 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     3,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
     4,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
     5,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
     6,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
     7,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
     8,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
     9,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
    10,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
    11,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
    12,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 30.000000 7814.000000 977.000000 
*******  TIDL_subgraphRtInvoke done  ******** 
In TIDL_runtimesPostProcessNet 

-------- Running Calibration in Float Mode to Collect Tensor Statistics --------
[=============================================================================] 100 %

------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------
[=============================================================================] 100 %

==================== [Quantization & Calibration Completed] ====================

========================== [Memory Planning Started] ==========================


------------------------- Network Compiler Traces ------------------------------
Successful Memory Allocation
Successful Workload Creation

========================= [Memory Planning Completed] =========================

Rerunning network compiler...
========================== [Memory Planning Started] ==========================


------------------------- Network Compiler Traces ------------------------------
Successful Memory Allocation
Successful Workload Creation

========================= [Memory Planning Completed] =========================

======================== Subgraph Compiled Successfully ========================



Model Output:  [array([[[[10., 10., 10., ..., 10., 10., 10.],
         [10., 10., 10., ..., 10., 10., 10.],
         [10., 10., 10., ..., 10., 10., 10.],
         ...,
         [10., 10., 10., ..., 10., 10., 10.],
         [10., 10., 10., ..., 10., 10., 10.],
         [10., 10., 10., ..., 10., 10., 10.]],

        [[10., 10., 10., ..., 10., 10., 10.],
         [10., 10., 10., ..., 10., 10., 10.],
         [10., 10., 10., ..., 10., 10., 10.],
         ...,
         [10., 10., 10., ..., 10., 10., 10.],
         [10., 10., 10., ..., 10., 10., 10.],
         [10., 10., 10., ..., 10., 10., 10.]],

        [[10., 10., 10., ..., 10., 10., 10.],
         [10., 10., 10., ..., 10., 10., 10.],
         [10., 10., 10., ..., 10., 10., 10.],
         ...,
         [10., 10., 10., ..., 10., 10., 10.],
         [10., 10., 10., ..., 10., 10., 10.],
         [10., 10., 10., ..., 10., 10., 10.]],

        [[10., 10., 10., ..., 10., 10., 10.],
         [10., 10., 10., ..., 10., 10., 10.],
         [10., 10., 10., ..., 10., 10., 10.],
         ...,
         [10., 10., 10., ..., 10., 10., 10.],
         [10., 10., 10., ..., 10., 10., 10.],
         [10., 10., 10., ..., 10., 10., 10.]]]], dtype=float32)]
************ in TIDL_subgraphRtDelete ************ 
 MEM: Deinit ... !!!
MEM: Alloc's: 28 alloc's of 115570421 bytes 
MEM: Free's : 28 free's  of 115570421 bytes 
MEM: Open's : 0 allocs  of 0 bytes 
MEM: Deinit ... Done !!!

Hi Ghassen,

Thanks for sending this over. Are you able to upgrade your SDK/TIDL TOOLS version? We had a couple of issues fixed for Gridsample from our 11.0 release, including one that could be related to the issue you might be seeing.

I will work on verifying if this fix is what you need, but wanted to make sure if you could upgrade as well.

Warm regards,

Christina

Hello Christina,

Thank you for your suggestion. Unfortunately, we’re unable to upgrade to the 11.0 release since this is a client project and SDK 10 is one of the project requirements.

Could you please provide a patch for SDK 10 to address this issue? If possible, it would also be great if you could include the fix for the TopK nodes in the same patch.

Best regards,
Ghassen

Hi Ghassen,

I am checking internally on the backport but could you verify which SDK version you are using, as well as which edgeai-tidl-tools version you are using?

You mentioned here that you are using 10.1 SDK

Ghassen souissi said:

sdk 10.1

whereas for the edgeai-tidl-tools, you are using 10_00_06_00

10.00.06.00 edgeai-tidl-tools will not work on SDK 10.1, which may be why you are seeing an issue when running on board if this is the case.

If you are using SDK 10.1, then you can use edgeai-tidl-tools version 11_00_07_00 which is the backport compatible for this SDK.

You can check the versions that match with the SDK version on the compatibility table found here: https://github.com/TexasInstruments/edgeai-tidl-tools/blob/master/docs/version_compatibility_table.md

Warm regards,

Christina

Hello Christina,

Sorry there was a mistake. The version of edgeai-tidl-tools that we are using is 10_01_04_00 which is the latest compatible version with sdk 10.01.00.04

Hi Ghassen,

thank you for the clarification! In this case, I recommend using 11_00_07_00  since this is backport compatible and see if this has the necessary gridsample bug fixes.

Warm regards,

Christina