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EDMA completion interrupts to ARM and DSP

SPRUGZ8 Chapter 1.6 shows the following interrupts going to the ARM and DSP:

ARM

12 EDMACOMPINT TPCC Region 0 DMA completion Interrupt

DSP

20 EDMAINT TPCC Region 1 DMA completion Interrupt

Chapter 7.4.9 states:

The EDMA3 interrupts are divided into 2 categories: transfer completion interrupts and error interrupts.
There are nine region interrupts, eight shadow regions and one global region. The transfer completion
interrupts are listed in Table 7-9. The transfer completion interrupts and the error interrupts from the
transfer controllers are all routed to the DSP and ARM interrupt controllers.
Table 7-9. EDMA3 Transfer Completion Interrupts
Name Description
EDMA3CC_INT0 EDMA3CC Transfer Completion Interrupt Shadow Region 0
EDMA3CC_INT1 EDMA3CC Transfer Completion Interrupt Shadow Region 1
EDMA3CC_INT2 EDMA3CC Transfer Completion Interrupt Shadow Region 2
EDMA3CC_INT3 EDMA3CC Transfer Completion Interrupt Shadow Region 3
EDMA3CC_INT4 EDMA3CC Transfer Completion Interrupt Shadow Region 4
EDMA3CC_INT5 EDMA3CC Transfer Completion Interrupt Shadow Region 5
EDMA3CC_INT6 EDMA3CC Transfer Completion Interrupt Shadow Region 6
EDMA3CC_INT7 EDMA3CC Transfer Completion Interrupt Shadow Region 7

Can I confirm that I need to use shadow regions and the ARM needs to use region 0 and the DSP needs to use region 1?

  • I was wondering the same, but I found this post by Brad:   http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/99/t/119494.aspx#425191


    Suggests that ARM is usually 0, DSP is usually 1.   This is what I"m going with at the moment, potentially to my own peril :)

    Matt