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TMS320F28386D-Q1: IPC Interrupts Set and Clear Flags

Ramon Martins
Prodigy 216 points
Part Number: TMS320F28386D-Q1
Other Parts Discussed in Thread: C2000WARE

Hi there,

I am using my own IPC message queue library based on the SDK's one (the only difference is that to inicializate the message queue data the cores exchange the address of the put and get buffer just to be safer).

Then when i start to put some stress on my application the CPU1 started to stopped receiving interrupts after some time. I manage to reproduce the error and read the registers on CPU1: 

These registers (IPCSTS.IPC1 = 1, PIEIFR.INTx10 = 0) indicate a lack of a Acknolegge action by the CPU1, the others configurations are pretty much the same when is properly working.

My interrupt code:

I'm acknowledging the flag every interrupt, so i wonder is this problem the result of the interaction of the SET(on the CM side) and ACK(on the CPU1 side) registers when set at the same time? I already tested to clear the flag before setting on the send message to queue function, and it was super effective, but in the SDK's library the function only sets the flag. Is there any documentation about the behaviour of these resgisters?

Best Regards,

Ramon.

  • 0
    TI__Mastermind 20975 points

    Hi Ramon,

    Your images are not visible on the forum post. Please reupload them again.

    Can you provide more information about the stress that is added on the application. How are you adding the stress to the system? Can you confirm that you are correctly acknowledging and clearing the flag.

    Regards,

    Ozino

  • 0 in reply to Ozino Odharo
    Prodigy 216 points

    Hi Ozino,

    I have reposted the images, please check it out.

    The "stress" that i mentioned is something like 200 messages per second, but this messages come by CAN so the interval ins't the same.

    I belive i'm clearing the flag correctly because the system works fine for some time, but after a while the CPU1 stops to receive message, to me seems like something related with the timing which these registers ack and set were set. if you have any documentations about the behavior of the ACK and SET  registers would be very help full, like if ACK(CPU1 core) and SET(CM core) are set at the very same time how the peripheral will behave?

    Thank you for your guidance.

  • 0 in reply to Ramon Martins
    TI__Mastermind 20975 points

    Hi Ramon,

    Thanks for the updates.

    I recommend checking out https://software-dl.ti.com/C2000/docs/C2000_Multicore_Development_User_Guide/ipc_communication.html# specifically sections 4.3,4.4 to ensure that you correctly acknowledging the interrupts correctly. 

    Can you confirm if you built your application on top of the examples provided in the IPC C2000Ware.

    Let me know once you've reviewed the above docs.

    Regards,

    Ozino