• State
  • Replies 8 replies
  • Subscribers 98 subscribers
  • Views 175 views
  • Users 0 members are here
Support feedback
Options
Options
Related

SK-AM62P-LP: SK-AM62P-LP: DSI Display not working (Waveshare 4-inch DSI LCD C)

Roman Lehmann
Prodigy 20 points
Part Number: SK-AM62P-LP
Other Parts Discussed in Thread: AM62P, AB15

Hello TI Team,

I’m currently trying to bring up a Waveshare 4-inch DSI LCD (C) display on the SK-AM62P-LP board, but so far without success.
Here’s the display in use:
Link https://www.waveshare.com/wiki/4inch_DSI_LCD_(C)

Waveshare confirmed that the official sources are:

  • Panel driver: drivers/gpu/drm/panel/panel-waveshare-dsi.c

  • Device tree overlay: overlays/vc4-kms-dsi-waveshare-panel-overlay.dts

I’ve ported the driver to the AM62P (kernel 6.6.58) and adjusted the device tree as shown below.

The panel is detected by DRM, and the connector reports as connected, but the display remains black.

cat /sys/class/drm/card0-DSI-1/status
connected

cat /sys/class/drm/card0-DSI-1/modes
720x720

modetest -M tidss -s 40@38:720x720
setting mode 720x720-60.03Hz on connectors 40, crtc 38

Backlight control works, no DSI or DSS errors appear in dmesg,
and modetest -M tidss confirms that connector, CRTC, and plane are correctly linked.

Panel timing (from driver):

.clock = 36500,
.hdisplay = 720,
.hsync_start = 760,
.hsync_end = 780,
.htotal = 800,
.vdisplay = 720,
.vsync_start = 744,
.vsync_end = 748,
.vtotal = 760,
.width_mm = 88,
.height_mm = 88,

Despite all this, no visible image appears on the display.

Questions:

  • Is this configuration (2 lanes, RGB888, 36.5 MHz pixel clock, 720×720) supported on the AM62P platform?

  • Are there any known limitations or specific DCS initialization commands required for custom MIPI-DSI panels on AM62P?

    Thank you very much for your support.


    Addtitional infos that can be relevant for you:


    modetest -M tidss -c -p

    modetest -M tidss -c -p
    Connectors:
    id      encoder status          name            size (mm)       modes   encoders
    40      39      connected       DSI-1           88x88           1       39
      modes:
            index name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot
      #0 720x720 60.03 720 760 780 800 720 744 748 760 36500 flags: ; type: preferred, driver
      props:
            1 EDID:
                    flags: immutable blob
                    blobs:

                    value:
            2 DPMS:
                    flags: enum
                    enums: On=0 Standby=1 Suspend=2 Off=3
                    value: 0
            5 link-status:
                    flags: enum
                    enums: Good=0 Bad=1
                    value: 0
            6 non-desktop:
                    flags: immutable range
                    values: 0 1
                    value: 0
            4 TILE:
                    flags: immutable blob
                    blobs:

                    value:

    CRTCs:
    id      fb      pos     size
    38      48      (0,0)   (720x720)
      #0 720x720 60.03 720 760 780 800 720 744 748 760 36500 flags: ; type: preferred, driver
      props:
            24 VRR_ENABLED:
                    flags: range
                    values: 0 1
                    value: 0
            27 CTM:
                    flags: blob
                    blobs:

                    value:
            28 GAMMA_LUT:
                    flags: blob
                    blobs:

                    value:
            29 GAMMA_LUT_SIZE:
                    flags: immutable range
                    values: 0 4294967295
                    value: 256

    Planes:
    id      crtc    fb      CRTC x,y        x,y     gamma size      possible crtcs
    31      38      48      0,0             0,0     0               0x00000001
      formats: AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12
      props:
            8 type:
                    flags: immutable enum
                    enums: Overlay=0 Primary=1 Cursor=2
                    value: 1
            30 IN_FORMATS:
                    flags: immutable blob
                    blobs:

                    value:
                            01000000000000001d00000018000000
                            01000000900000004152313241423132
                            52413132524731364247313641523135
                            41423135415232344142323452413234
                            42413234524732344247323441523330
                            41423330585231325842313252583132
                            58523135584231355852323458423234
                            52583234425832345852333058423330
                            59555956555956594e56313200000000
                            ffffff1f000000000000000000000000
                            0000000000000000
                    in_formats blob decoded:
                             AR12:  LINEAR(0x0)
                             AB12:  LINEAR(0x0)
                             RA12:  LINEAR(0x0)
                             RG16:  LINEAR(0x0)
                             BG16:  LINEAR(0x0)
                             AR15:  LINEAR(0x0)
                             AB15:  LINEAR(0x0)
                             AR24:  LINEAR(0x0)
                             AB24:  LINEAR(0x0)
                             RA24:  LINEAR(0x0)
                             BA24:  LINEAR(0x0)
                             RG24:  LINEAR(0x0)
                             BG24:  LINEAR(0x0)
                             AR30:  LINEAR(0x0)
                             AB30:  LINEAR(0x0)
                             XR12:  LINEAR(0x0)
                             XB12:  LINEAR(0x0)
                             RX12:  LINEAR(0x0)
                             XR15:  LINEAR(0x0)
                             XB15:  LINEAR(0x0)
                             XR24:  LINEAR(0x0)
                             XB24:  LINEAR(0x0)
                             RX24:  LINEAR(0x0)
                             BX24:  LINEAR(0x0)
                             XR30:  LINEAR(0x0)
                             XB30:  LINEAR(0x0)
                             YUYV:  LINEAR(0x0)
                             UYVY:  LINEAR(0x0)
                             NV12:  LINEAR(0x0)
            33 zpos:
                    flags: range
                    values: 0 1
                    value: 0
            34 COLOR_ENCODING:
                    flags: enum
                    enums: ITU-R BT.601 YCbCr=0 ITU-R BT.709 YCbCr=1
                    value: 0
            35 COLOR_RANGE:
                    flags: enum
                    enums: YCbCr limited range=0 YCbCr full range=1
                    value: 1
            36 alpha:
                    flags: range
                    values: 0 65535
                    value: 65535
            37 pixel blend mode:
                    flags: enum
                    enums: Pre-multiplied=0 Coverage=1
                    value: 0
    41      0       0       0,0             0,0     0               0x00000001
      formats: AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12
      props:
            8 type:
                    flags: immutable enum
                    enums: Overlay=0 Primary=1 Cursor=2
                    value: 0
            30 IN_FORMATS:
                    flags: immutable blob
                    blobs:

                    value:
                            01000000000000001d00000018000000
                            01000000900000004152313241423132
                            52413132524731364247313641523135
                            41423135415232344142323452413234
                            42413234524732344247323441523330
                            41423330585231325842313252583132
                            58523135584231355852323458423234
                            52583234425832345852333058423330
                            59555956555956594e56313200000000
                            ffffff1f000000000000000000000000
                            0000000000000000
                    in_formats blob decoded:
                             AR12:  LINEAR(0x0)
                             AB12:  LINEAR(0x0)
                             RA12:  LINEAR(0x0)
                             RG16:  LINEAR(0x0)
                             BG16:  LINEAR(0x0)
                             AR15:  LINEAR(0x0)
                             AB15:  LINEAR(0x0)
                             AR24:  LINEAR(0x0)
                             AB24:  LINEAR(0x0)
                             RA24:  LINEAR(0x0)
                             BA24:  LINEAR(0x0)
                             RG24:  LINEAR(0x0)
                             BG24:  LINEAR(0x0)
                             AR30:  LINEAR(0x0)
                             AB30:  LINEAR(0x0)
                             XR12:  LINEAR(0x0)
                             XB12:  LINEAR(0x0)
                             RX12:  LINEAR(0x0)
                             XR15:  LINEAR(0x0)
                             XB15:  LINEAR(0x0)
                             XR24:  LINEAR(0x0)
                             XB24:  LINEAR(0x0)
                             RX24:  LINEAR(0x0)
                             BX24:  LINEAR(0x0)
                             XR30:  LINEAR(0x0)
                             XB30:  LINEAR(0x0)
                             YUYV:  LINEAR(0x0)
                             UYVY:  LINEAR(0x0)
                             NV12:  LINEAR(0x0)
            43 zpos:
                    flags: range
                    values: 0 1
                    value: 1
            44 COLOR_ENCODING:
                    flags: enum
                    enums: ITU-R BT.601 YCbCr=0 ITU-R BT.709 YCbCr=1
                    value: 0
            45 COLOR_RANGE:
                    flags: enum
                    enums: YCbCr limited range=0 YCbCr full range=1
                    value: 1
            46 alpha:
                    flags: range
                    values: 0 65535
                    value: 65535
            47 pixel blend mode:
                    flags: enum
                    enums: Pre-multiplied=0 Coverage=1
                    value: 0

    The display is not showing a picture.

     kmstest --device="/dev/dri/card0"

    Connector 0/@40: DSI-1
      Crtc 0/@38: 720x720@60.03 36.500 720/40/20/20/? 720/24/4/12/? 60 (60.03) 0x0 0x48
      Plane 0/@31: 0,0-720x720
        Fb 50 720x720-XR24
    press enter to exit



  • 0
    TI__Genius 9570 points

    Hi,
    Thanks for the detailed observations.

    Can you try increasing the blanking period in timing parameters. For reference, please take a look at mazel's reply just before the first reply marked as resolved: RE: AM62L: dsi_p_clk has no rate  .


    Roman Lehmann said:
    Is this configuration (2 lanes, RGB888, 36.5 MHz pixel clock, 720×720) supported on the AM62P platform?

    Yes, this can be supported.

    Roman Lehmann said:
    Are there any known limitations or specific DCS initialization commands required for custom MIPI-DSI panels on AM62P?

    It has been seen multiple times that increasing blanking periods from the datasheet ones helps the case. For an example initialisation sequence on 6.6 kernel, please refer static const struct ili9881c_instr mf_070zimacaa0_init[]

  • 0 in reply to Divyansh Mittal
    Prodigy 20 points

    Hi Divyansh,

    thanks for the pointers. Quick summary of what I tried and observed:

    The original vendor timings for the 4" DSI panel in the driver are:

    .clock = 50000,
.hdisplay = 720,
.hsync_start = 720 + 32,
.hsync_end   = 720 + 32 + 200,
.htotal      = 720 + 32 + 200 + 120,

.vdisplay = 720,
.vsync_start = 720 + 8,
.vsync_end   = 720 + 8 + 4,
.vtotal      = 720 + 8 + 4 + 16,

    But I can’t use them because as soon as HTOTAL > ~1000, the driver rejects the mode with:

    failed to set mode: Function not implemented

    That’s why I tested “near-original” variants with HTOTAL ≤ 1000. These are accepted by the driver, but I still get no picture:

    # Keep V timings as vendor; shrink HTOTAL to 960 (HSW 64, HBP 144)
modetest -D 30220000.dss -s 40@38:720,752,816,960,720,728,732,748-62 -P 31@38:720x720+0+0@XR24 -v

# Keep V timings; HTOTAL 896 (HSW 64, HBP 80)
modetest -D 30220000.dss -s 40@38:720,752,816,896,720,728,732,748-62 -P 31@38:720x720+0+0@XR24 -v

# Keep HTOTAL 960; sweep HFP while holding HTOTAL constant
modetest -D 30220000.dss -s 40@38:720,748,812,960,720,728,732,748-62 -P 31@38:720x720+0+0@XR24 -v   # HFP=28, HSW=64, HBP=168
modetest -D 30220000.dss -s 40@38:720,756,820,960,720,728,732,748-62 -P 31@38:720x720+0+0@XR24 -v   # HFP=36, HSW=64, HBP=160

# Give more vertical blank (VBP stays ≤255); HTOTAL 960
modetest -D 30220000.dss -s 40@38:720,752,816,960,720,728,732,900-60 -P 31@38:720x720+0+0@XR24 -v

    Could you confirm whether there’s an HTOTAL / porch constraint on the AM62P DSI path?

    Do you have any additional suggestions I could try next?

    Regarding your note about an initialization sequence: I checked the panel driver and there is no initialization phase—no DCS commands are sent at all. So I think we can ignore this.

    BR,
    Roman

  • 0 in reply to Roman Lehmann
    TI__Genius 9570 points

    Hi,
    Can you add the following debug prints in the driver and share the logs:

    diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c

index 8f57919cd74e..6f20b8925d5e 100644

--- a/drivers/phy/cadence/cdns-dphy.c

+++ b/drivers/phy/cadence/cdns-dphy.c

@@ -153,8 +153,11 @@ static int cdns_dphy_get_pll_cfg(struct cdns_dphy *dphy,
  cfg->hs_clk_rate = div_u64((u64)pll_ref_hz * cfg->pll_fbdiv,                                
                           2 * cfg->pll_opdiv * cfg->pll_ipdiv);                              

+   trace_printk("DT: cfg->pll_ipdiv : %d, cfg->pll_opdiv : %d, cfg->pll_fbdiv : %lld, dlane_bps : %lld, pll_ref_hz : %lld cfg->hs_clk_rate : %lld\n", cfg->pll_ipdiv,  cfg->pll_opdiv, cfg->pll_fbdiv, dlane_bps, pll_ref_hz, cfg->hs_clk_rate); `
 
* `  return 0;                                                                                    `

}  

@@ -929,6 +952,7 @@ static long cdns_dsi_round_pclk(struct cdns_dsi *dsi, unsigned long pclk)       
        ret = phy_validate(dsi->dphy, PHY_MODE_MIPI_DPHY, 0, &phy_opts);                            
        if (ret)                                                                                    
                return ret;                                                                         
+       trace_printk("orig pclk : %lld, calc pck : %lld hs_clk_rate : %lld", pclk, div_u64((u64)phy_opts.mipi_dphy.hs_clk_rate * nlanes, bitspp), (u64)phy_opts.mipi_dphy.hs_clk_rate);
                                                                                                    
        return div_u64((u64)phy_opts.mipi_dphy.hs_clk_rate * nlanes, bitspp);

    Patch may not apply directly and will need to applied manually.

  • 0 in reply to Divyansh Mittal
    Prodigy 20 points

    Hi Divyansh,

    on my kernel version
    a7758da17c28 (HEAD -> ti-linux-6.6.y, tag: cicd.scarthgap.202412030400, tag: 10.01.10, origin/ti-linux-6.6.y) driver core: fw_devlink: Stop trying to optimize cycle detection logic
    there’s no function named cdns_dphy_get_pll_cfg in cdns-dphy.c. I do have cdns_dsi_get_dphy_pll_cfg, and that’s where I added the debug prints.

    I also couldn’t find cdns_dsi_round_pclk — neither in this tree nor in the latest TI kernel (ti-linux-6.12.y). It seems you’re referring to a newer kernel or a different patch set. Could you point me to the exact branch/commit or patch series?

    DEBUG output (bad case):

    modetest -D 30220000.dss -s 40@38:720,752,952,1072,720,728,732,748-62 -P 31@38:720x720+0+0@XR24 -v
trying to open device 'i915'...done
[  189.078240] DT 6 Aug: cfg->pll_ipdiv : 2, cfg->pll_opdiv : 4, cfg->pll_fbdiv : 384, dlane_bps : 600000000, pll_ref_hz : 25000000
setting mode custom720x720-62.00Hz on connectors 40, crtc 38
failed to set mode: Function not implemented
testing 720x720@XR24 overlay plane 31
[  189.087243] DT 6 Aug: cfg->pll_ipdiv : 2, cfg->pll_opdiv : 4, cfg->pll_fbdiv : 382, dlane_bps : 596580000, pll_ref_hz : 25000000
select timed out or error (ret 0)

    DEBUG output (good case):

    modetest -D 30220000.dss -s 40@38:720,744,764,800,720,744,748,760-60 -P 31@38:720x720+0+0@XR24 -v
trying to open device 'i915'...done
[  255.998292] DT 6 Aug: cfg->pll_ipdiv : 2, cfg->pll_opdiv : 4, cfg->pll_fbdiv : 384, dlane_bps : 600000000, pll_ref_hz : 25000000
setting mode custom720x720-60.00Hz on connectors 40, crtc 38
[  256.007290] DT 6 Aug: cfg->pll_ipdiv : 2, cfg->pll_opdiv : 4, cfg->pll_fbdiv : 281, dlane_bps : 437760000, pll_ref_hz : 25000000
[  256.015370] DT 6 Aug: cfg->pll_ipdiv : 2, cfg->pll_opdiv : 4, cfg->pll_fbdiv : 281, dlane_bps : 437760000, pll_ref_hz : 25000000
testing 720x720@XR24 overlay plane 31
freq: 60.16Hz

    Thanks,
    Roman

  • 0 in reply to Roman Lehmann
    TI__Genius 9570 points

    Hi,
    Sorry for the confusion. The second function is present in the kernel, just in a different file: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c?h=ti-linux-6.12.y#n925 

  • 0 in reply to Divyansh Mittal
    Prodigy 20 points

    Hi,

    in my used Kernel version there is no such a function:
    git.ti.com/.../cdns-dsi-core.c

  • 0 in reply to Roman Lehmann
    TI__Genius 9570 points

    Hi,
    Just realised you are on 6.6 kernel. There have been a significant number of patches put in place for DSI driver from 6.6 to 6.12 without which there can be pixel clock discrepancies for some bridges. I would strongly recommend you to switch to 6.12 and then test your DSI display.

  • 0 in reply to Divyansh Mittal
    Prodigy 20 points

    Hi Divyansh,

    thanks for the heads-up. You’re right—we’re on a 6.6 kernel. We’ve stayed there because our current TI Yocto stack depends on Qt 5, while the latest TI SDK has already moved to Qt 6.

    I’ll pull the newest SDK with the 6.12 kernel to bring up the DSI display and verify the pixel clock behavior. If that works, I’ll look into backporting the relevant DSI patches to our preferred Qt 5–based tree (or consider moving forward accordingly).

    Appreciate the guidance—will update you with the results.

    Best,
    Roman