TPS40210: TPS40210 Output issue

Part Number: TPS40210


We are currently using the TPS40210 to convert to 52V, but we’ve observed instability issues. The measured waveform and circuit are shown below. Could you please advise what might be causing this problem?

In the figure, the yellow trace represents the MOSFET gate, and the blue trace represents the drain.

  • Hi Jacky,

    Thanks for using the e2e forum.
    This boost design is build for VIN 5V and VOUT 52V, correct?

    Can you give me the maximum load conditions for this application?

    The load parameter is important for calculating if the application runs in DCM or CCM, and what stability is to be expected based on the selected compensation.
    We can then also calculate if there could be problems with maximum duty cycle (minimum off-time).
    For CCM, I would expect a duty cycle of ~90%.

    Thanks and best regards,
    Niklas

  • The average load power is currently 6 W.

  • Hi Jacky,

    Thanks for the update.
    There are two major points I see for this design:

    1. The design runs in CCM with 90% duty cycle. The calculated off-time at 600kHz is ~160ns.
    The device specification for minimum off-time is 150ns (typ) / 200ns (max).
    So the application runs very close to the limit of minimum off-time.
    To operate the application in DCM to reduce the duty cycle, a smaller inductance would be necessary (e.g. 2uH or smaller), which would then increase the peak inductor currents.

    2. The filter at the current sense pin (ISNS) is rather large. R27 1kOhm + C15 220nF.
    I would recommend to reduce the C15 capacitor to avoid filtering the sensed current signal itself, which comes with risk of instability.
    E.g. 100pF.

    I would recommend to change the filter capacitor first to see if the behavior improves.
    If this is not sufficient, it could be possible that the device cannot support this high duty cycle, so a DCM design would be necessary.

    Best regards,
    Niklas