c6678 PCIEboot

IBL is only for the PLL fix as for as the boot is concerned. If you are using our EVM, the i2c EEPROM 0x51 has the ibl flashed. So you don't need to do anything unless you have already reflashed the EEPROM. If you want to try out in your custom board, then you can use the simple PLL fix that we have in the external wiki page. The link is below:

http://processors.wiki.ti.com/images/4/4d/SecondaryBoot_PLLfix.zip

Thanks,

Arun.

Just to add a little more information. The PLL issue is listed in the errata, and only effects Revision 1.0 Si.  This is fixed on Rev 2.0 Si which we have begun sampling.  An updated version of the errata will be coming out next week.

Best Regards,

Chad

Hi,

There is no EEPROM in my own board, how do I use the PCIe boot?

Thanks.

Andy,

You would need to wait until you have Revision 2.0 of the Si (sampling now.) To ensure you do no experience the bug from Advisory #8 documented in the Errata, on 1.0 Si, were the PLL's do not lock, then you will have to implement the workaround as mentioned.

Best Regards,

Chad

Hi Arun,

             I want to use the SecondaryBoot_PLLfix to does the PLL reset workaround in my own board.

             How to build SecondaryBoot_PLLfix project and download it to eeprom?

             Is there any detail introduction about SecondaryBoot_PLLfix?

             I may found someting wrong in the SecondaryBoot_PLLfix project:

            in secondaryBoot_PLLfix\Utils\utils_src\Makefile

    all: b2ccs.exe b2i2c.exe ccs2bin.exe bconvert64x

 bin2ccs.exe: bin2ccs.c
 gcc -g -o bin2ccs bin2ccs.c

b2ccs.exe: b2ccs.c
	gcc -o b2ccs b2ccs.c

ccs2bin.exe: ccs2bin.c
	gcc -o ccs2bin ccs2bin.c

bconvert64x: bconvert64x.c
	gcc -o bconvert64x bconvert64x.c

You are correct. i am attaching the updated Makefile. PLease use this. I will update the zip file soon.

As for the instruction, we have only the README and the build.bat that will show how to create EEPROM image. To load the image use the instructions in the EEPROM writer from MCSDK. Try using the latest version has it is proved to be more stable.

Thanks,

Arun.

Hello,

 TMS320C6678 EVM installed in АМС slot

The command ‘insmode pciedemo.ko’  calls log:

root@Debian:/home/dm/hello_world# insmod pcie.ko
[ 54.805033] Finding the device....
[ 54.808670] Found TI device
[ 54.811457] TI device: vendor=0x0000104c, dev=0x0000b005, drv=0x00000000, irq=0x0005, bus=0xf6c5e600
[ 54.820595] Reading the BAR areas....
[ 54.825694] Enabling the device....
[ 54.829297] pci 0000:0a:00.0: PCI->APIC IRQ transform: INT A -> IRQ 17
[ 54.835844] Access PCIE application register ....
[ 54.840542] Boot entry address is 0x1082cc00
[ 54.845982] Total 4 sections, 0xd748 bytes of data written to core 0
[ 54.911022] Boot entry address is 0x8000cc00
[ 54.916183] Total 4 sections, 0xd89c bytes of data written to core 9
[ 54.922532] sys_init_module: 'pciedemo'->init suspiciously returned 1, it should follow 0/-E convention
[ 54.922535] sys_init_module: loading module anyway...
[ 54.936952] Pid: 1446, comm: insmod Not tainted 2.6.32-5-686 #1
[ 54.942862] Call Trace:
[ 54.945311] [<c1057ce1>] ? sys_init_module+0x127/0x1d7
[ 54.950535] [<c10030fb>] ? sysenter_do_call+0x12/0x28
root@Debian:/home/dm/hello_world# 

What is this?

Hi,

    we have Revision 2.0 of the Si now.

    we load the code by pcie,but it can not boot(situation same as  1.0 Si).

   when  the code is loaded  completed,then write the start address to magic address. but the 6678 can't boot.

   we moved  PC pointer  to start address by Emulator ,then it can boot(it's mean the code is ok)

My question is : if the Revision 2.0 of the Si can boot from PCIE not use EEPROM?

My PCIE boot configure as bellow(Please check it):

LENDIAN＝1
BOOT[2:0]=100(PCI)
BOOT[8:5]=0000   32bit
BOOT[12:10]=011  100M
BOOT9,BOOT4,BOOT3Reserved =>1

PCIESSEN=1
PCIESSMODE[1:0]=01

BR

wuxiao