AM3352: DDR power on timing adjustment

I followed the modification in this link ,but the delay time was still the same 

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1302074/am3354-delay-between-ddr_cke-and-ddr_reset-configuration-in-spl/4974319#4974319

The patch should have fixed this as proven in the other thread.  I'm not sure why it is not producing the same results.  Ensure that the patch is applied properly, and that the new image is executing correctly on your board. 

If you still can't get it working, send the ddr.c file with your modifications.

Regards,

James

Hi，We just tested the actual delay value, and after the modification, the delay time became 544us. Before the modification, it was 140us, indicating that the modification has taken effect. However, I checked the values in the DDR and found that they are still very random. It seems that the DDR has not been cleared. Have you encountered similar problems before

The data is as follow，very random

Hi Zhang, the intialization of DDR does not include clearing the contents of the memory.  In fact, it is expected to see random data in a memory that has just been initialized.  Check to make sure you can successfully read/write the memory, especially using linux memtester for stress testing across your expected operating temperature.  If this is successful, you can conclude you have a robust DDR configuration..  

Regards,

James