Hi TI Experts,
Customer is building their own TDA4AEN development board.
And customer selects PDN-7D.DES for their PDN design.
In the following development guide, customer has below two questions:
https://www.ti.com/lit/po/sprt775/sprt775.pdf?ts=1761233822822
1: For PDN-7D.DES design they selected, could they still follow the Table 12 as the reference for power on sequencing?
2: When the PMIC starts, it reads the status of RS2, i.e., VMON1. However, VMON1’s power comes from an independent buck output, whose enable signal is PMIC’s GPIO5. Here, VMON1 is internally a comparator with VSENSE at 0.85 V and a logic level of 1, so the threshold is set to 0.85 V. Yet the external buck is not enabled, causing the reading to be close to 0 V, and the threshold is set to 0.75 V. Meanwhile, the PDN VSEL setting of 7D.DES for the external buck is 0.85 V. Doesn't this cause a detection error?
Thanks,
Kevin