Clarification: Figure 8-24--Routing rules mirroried DDR3

Update: Corrected an error in the title, the figure in question is Figure 8-28, the table is Table 8-24 

Clarification: Figure 8-28--Routing rules mirrored DDR3

My question is regarding the interpretation of the diagram on page 196 of the SPRS614A document. We are currently bringing up the first prototype of our board with a DM8168 SoC, and I am in the process of routing the DDR3 of the first major revision to the design. We designed the first prototypes as an exact copy of EVM revision E board, at least as far as the DDR3 is concerned. For the revision I am working on now, we are trying to implement a DDR3 system more suited to our needs, much more compact and with all of the traces buried. In October and November, I came up with a design using a pencil and calculator that I believe complies with all of the rules in section 8.3.2 of the SPRS614a document. It has ten layers and four x16 DDR3 memories instead of 8 x8. Each EMIF has two chips mounted in a mirror configuration, one on TOP, one on BOTTOM. As I was routing the design in our CAD package, I started to realize that Figure 8-28 is somewhat open to interpretation (to me anyway).

See the attached PDF for my attempt to represent my question in a graphical manner. It is clearly stated in Table 8-24 that A3 (the length between the stubs to the pins of the two devices) can be no more than 660 mils, and it even gives a special looser limit of 125 mils for the A3 skew in the mirrored configuration. But what is not specified (at least not in any way that I can distinguish) is whether it is allowed to have one device electrically "before" the other in some traces and electrically "after" in others. Figure 8-28 gave me the impression that it was allowed, because it is a natural consequence of the way the stubs are drawn in the diagram. In my annotation to Figure 8-28 you will find a section view that shows the two possibilities. In Case 1, the trace arrives on an inner layer from the Netra on transmission line A2 and hits a via where it splits, and the stub connects to the device on TOP (U21). The trace continues on as transmission line A3 to the next via where it splits and the stub connects to the device on BOTTOM (U22). In Case 2, everything is the same except the traces arrives to U22 BEFORE it gets to U21. My guts tell me that this is exactly what was intended in mirrored routing, but my guts have been known to be wrong.  Can someone please confirm that this is correct? Is it allowed to route the stubs to the closest possible connection point, even if that means that half of the signals will reach U21 first and half will reach U22 first? Thank you.

3884.DDR3_mirror_clarification.pdf

For DDR3, the address bus is a fly-by topology.  The address signals need to go from the controller to the first DDR device, to the second DDR device and then to a series terminator to VTT.  The order is important – it has to be the same for each CK/ADDRESSS/CTRL bit otherwise there will be issues with the DDR3 R/W leveling.  Recall that the R/W leveling measures and compensates for differing command versus data delay for each DDR chip.

For this case, the board has the DDR devices mirrored, which is an acceptable configuration.  One thing that makes this configuration tricky is maintenance of the address bus topology.  The PCB layout designer must choose which device to route to first and then maintain that consistently across all the CK/ADDR/CTRL bits.  With mirrored devices and advanced PCB technology it is possible to drive some of the topology elements to extremes where they effectively get zeroed out.

The key to ensuring a mirrored DDR3 PCB design is TI spec compliant is to maintain skew requirements and causality between the lower and upper data words.  This is tricky because the causality is dictated by DDR3 R/W leveling.  The causality issue is complicated if one zeros out the length of the A3 segment from the data sheet spec.  There is nothing in the spec that disallows a zero length A3.  A real “zero length A3” can have a length of up to 125 mils, due to skew allowances.  Thus, if one limits the maximum A3 segment to 125 mils, and maintains the AS length maximums of 100 mils, then the ordering of the DDR address pins does not matter.  However once an A3 segment length exceeds 125 mils, the minimum segment length for A3 is non-zero and the order of the DDR address pins does matter.

Refer to the topology figures out of the DM816x datasheet:
Figure 8-24. ADDR_CTRL Topology for Two DDR3 Devices
Figure 8-28. ADDR_CTRL Routing for Two Mirrored DDR3 Devices

Also refer to the non-mirrored routing (Fig 8-26) for clarity.  Figure 8-28 is electrically same, with the complication that the two DDR devices overlap each other.  Note that in Figure 8-26 it is practically impossible to zero out the A3 segment, while in Figure 8-28 it is by using the available skew margin.

Contrast this with a non-zero length design:

The catch is you cannot have both a “A3 Zero Length” and “A3 Non-zero Length” topology in one design.  You must choose one or the other.