AM67A: Three Independent Video Outputs with DSI and LVDS

Ryan Davitt

Part Number: AM67A
Other Parts Discussed in Thread: AM62P, AM67

Hello,

My customer is looking to implement a three screen system using only DSI and LVDS (DPI pinout not currently available on their board).

Two questions:

1) Can there be two separate video pipelines connected to LVDS when in 2 output, 4-Lane (Single Link) mode. I see some answers here for AM62 saying no and AM62P saying yes, but nothing really on AM67A.

2) Is there a second DSI port available to generate an additional screen output thru DSI? This is a direct question from the customer. My understanding is that there is only 1 DSI port on the AM67A, but I wanted to double check before answering that question.

Best,

Ryan

11 days ago

0 Divyansh Mittal 11 days ago

TI__Genius 9610 points

Hi,
1) Yes, 2x independent Single-Link (4 lane) OLDI is supported.
2) DSI can be used in addition to 2x SL-OLDI, but there will be some restriction on max pixel clock available for DSI (165MHz)

DSS IP is exactly same between AM62P, AM67 and AM67A.
Please refer https://www.ti.com/lit/an/sprads3/sprads3.pdf for all the possible display configurations and limitations.

0 Ryan Davitt 10 days ago in reply to Divyansh Mittal

TI__Prodigy 570 points

Hey Divyansh,

Thanks for the support. They were able to get the OLDI configuration to load on the AM67A properly. However, OLDI1 output never goes high, "as if the pins were disabled."

I've told them to look at the registers for DSS0 and DSS1's VP1 and VP2 for OLDI configurations to check the system's status.

In the meantime, any feedback here? Are there any other adjustments that need to be made outside of the devicetree code that is given in the app note you sent?

Best,

Ryan

0 Divyansh Mittal 10 days ago in reply to Ryan Davitt

TI__Genius 9610 points

Hi,
Just realised that AM67 SDK hasn't released 11.1 yet. Please add the following patch:
https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/commit/?h=ti-linux-6.12.y&id=670fcdf73e85f67e0917cdf0cc6ec4f5fcf43392

0 Ryan Davitt 9 days ago in reply to Divyansh Mittal

TI__Prodigy 570 points

Hey Divyansh,

I pointed the customer to our AM62P debugging FAQ here on E2E, and they used some of those commands to find the bug. Looks like the root of the problem was around the DSI0 example, which uses the DSS1 clock and VP1, conflicting with the 2x single link OLDI configuration.

I have passed along the patch you sent, but it sounds like they have their system working currently.

Thanks for the support!

Ryan

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AM67A: Three Independent Video Outputs with DSI and LVDS