DM8168 Discrete SYNC Capture problem

Hi,

Few questions and clarifications to sort out the issue.

1. You have ES2.0 or ES1.1 silicon.

2. On ES1.1 silicon we have an errata for discrete sync which is as follows. So please make sure you have taken care of it.

"The VIP parser requires that the ACTVID signal is active for all lines of the incoming data, including the vertical blanking region."  You can refer to errata at http://www.ti.com/lit/er/sprz329a/sprz329a.pdf

3. In case 2 where you are getting bad images, can you please crop the image by one line and try.You can use scalar to crop image.

Regards,

Hardik Shah

Hi

Thank you for reply.

1.I have use ES1.1 silicon I guess.(I read cpu id from addr 0x48140600)

2.I have read that datasheet.But I do Not quite understand.that mean ES1.1 and ES1.0 silicon can not use discrete sync capture picture data?(when use some external video decoder)

3. I had run TI Demo in DVRRDK_01.06.00.11 SDK to get that images. (capture -> SC-> H264 encode -> write H264 FILE  or capture -> H264 encode -> write H264 FILE ) the demo file is Multichhd_vcap_venc_vdis.c

Can you help me to confirm that problem?

Ths

Regards

Hi,

I again read your thread. How are you configuring TVP7002 for 1280X1024 resolution. I think TVP7002 driver doesn't support 1280X1024 resolution. That worked may be because of your luck. Can you please confirm with RDK team that 1280X1024 is a supported resolution over TVP7002. I guess its not.

Regards,

Hardik Shah

hi

 thank you for you reply!

 1280X1024 resolution I have confirmed before my test. The driver is supported that resolution.

The driver code like this

/**
 *  \brief List of values used for SXGA@60 settings.
 *  Caution: The value list order should match with the address list order.
 */
static UInt8 gTvp7002ValueSxga60[] =
{
    0x69u,              /* HPLL_DIVIDER_MSB         */
    0x80u,              /* HPLL_DIVIDER_LSB         */
    0xA0u,              /* HPLL_CTRL                */
    0x80u,              /* HPLL_PHASE_SELECT        */
    0x06u,              /* CLAMP_START              */
    0x10u,              /* CLAMP_WIDTH              */
    0x20u,              /* HSYNC_OUT_WIDTH          */
    0x52u,              /* SYNC_CTRL1               */
    0x01u,              /* HPLL_PRE_COAST           */
    0x00u,              /* HPLL_POST_COAST          */
    0x00u,              /* MISC_CTRL3               */
    0xAAu,              /* IN_MUX_SELECT1           */
    0x6Au,//0xC2u,//0x6Au,              /* IN_MUX_SELECT2           */
    0x08u,              /* HSOUT_OUT_START          */
    0x00u,              /* MISC_CTRL4               */
    0x50u,              /* ADC_SETUP                */
    0x18u,              /* ALC_PLACEMENT            */
    0x80u,              /* AVID_START_PIXEL_LSB     */
    0x01u,              /* AVID_START_PIXEL_MSB     */
    0x86u,              /* AVID_STOP_PIXEL_LSB      */
    0x06u,              /* AVID_STOP_PIXEL_MSB      */
    0x04u,              /* VBLK_FLD0_START_OFFSET   */
    0x00u,              /* VBLK_FLD1_START_OFFSET   */
    0x2Au,              /* VBLK_FLD0_DURATION       */
    0x00u,              /* VBLK_FLD1_DURATION       */
    0x00u,              /* FBIT_FLD0_START_OFFSET   */
    0x00u               /* FBIT_FLD1_START_OFFSET   */
};

thank you! 

Hi,

TVP7002 may be supporting SXGA but i am not sure driver is configured for SXGA embedded sync. This is because V4L2 capture driver is configured for embedded sync.  If TVP7002 is outputting discrete sync then VIP capture wont received it since its configured for embedded sync reception. You can refer to following document on how to configure V4L2 capture driver for discrete sync reception. 

http://processors.wiki.ti.com/index.php/DM81xx_AM38xx_Adding_External_Decoders_to_V4L2_Capture_Driver

Regards,

Hardik Shah

Hi HardikShah,

Thank for your answer, but can't you give a more constructive answer instead of sending me to read the wiki of adding external decoders to V4L2?
For example how to configure VIP capture to receive discrete sync?

Thanks,
Gabi 

Hi,

Even if i give constructive answer it will be directly from wiki.  Thats why we have created wiki to help more people. You can read that and come up with your specific questions and i will be happy to address that.

Regards,

Hardik Shah

Hi HardikShan,


I'll start to support capture for 1280x1024@67fps through VGA (TVP7002 chip) on DM8168, but I'm not aware if it supports that framerate is possible.

Have you tried to capture using no standard framerate like 67Hz on DM8168?

I'm using linux-2.6.37-psp04.04.00.01

Best Regards
Angel

Hello,

Refer to :

BR

Margarita