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TDA4VE-Q1: Recommend DRAM size / DRAM ranks usage

Rodrigo Badia
Prodigy 10 points

Part Number: TDA4VE-Q1
Other Parts Discussed in Thread: DRA829

Is there a guideline for recommend DRAM size based on the target application for TDA4VE88?

I'd like some rough numbers considering 2 scenarios:

  • 4x 3MPixel @ 60fps cameras with pedestrian detection.
  • 4x 3MPixel @ 60fps cameras with Surround Vision and pedestrian detection.

Also, this SoC has two DRAM buses / ranks. Is it mandatory to use both considering these applications? 

Why the EVM schematics (PROC078E8C(001)_SCH) has only 1 DRAM bus?

 

Thank you in advance,

 

Rodrigo

  • 0
    TI__Mastermind 44920 points

    Hi Rodrigo,

    I am answering from hardware side (not related to your use case).

    Rodrigo Badia said:
    Why the EVM schematics (PROC078E8C(001)_SCH) has only 1 DRAM bus?

    TDA4VE supports 2 DDR sub-systems (DDRSS0 and DDRSS1). Each DDRSS supports 2 ranks (though only a single packaged LPDDR4 memory per DDRSS).

    The J721S2 EVM (https://www.ti.com/tool/J721S2XSOMXEVM) uses both DDRSS0 and DDRSS1, and supports TDA4VE devices.

    Board design "PROC078E8C" is for the J721E EVM , which is used for TDA4VM / DRA829 parts.

    Rodrigo Badia said:
    Also, this SoC has two DRAM buses / ranks. Is it mandatory to use both considering these applications? 

    You can use "DDRSS0 only" if you only need 1x DDRSS. It is not mandatory to use both DDRSS (from hardware perspective). Please note that some DDR IO of unused DDRSS may have specific board requirements. Please refer to the device datasheet (section "Connection for Unused Pins"). 

    Regards,
    Kevin