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DSP/BIOS 5 cache coherency question

hezi halifa
Prodigy 220 points

 

Hi,

I have  L1 and L2 cache configured in TCF.   As I understan, during bootload of the program,  L1 & L2 caches are disabled.

 I am not sure that  "cache disable" means that it is invalidated, and so after bootloading a new software in DSP,  I would like to ensure that the new downloaded software

will not obtain any old caching. so, would like to  invalidate the L2 cache right after bootloading. 

another question:  since L2 cache was configured in TCF,  is it enabled right after bootloading. can I safely use a function like CACHE_wbInvAllL2 right after bootloading?

thank you

 Hezi.

 

  • 0
    TI__Mastermind 18320 points

    What device are you asking about?

    What version of DSP/BIOS are you using?

  • 0 in reply to David Friedland
    Prodigy 220 points

     

    the device is DSP 6748, and I am using DSP/BIOS 5,

    thank you

     Hezi.

     

     

     

     

     

  • 0 in reply to hezi halifa
    TI__Mastermind 26780 points

    Hezi,

    Can you please post how you are configuring CACHE in your .tcf file?

    Is this a new application, or are you modifying/porting an older one?

    When using DSP/BIOS we strongly encourage people to use the BCACHE APIs provided with DSP/BIOS (see section 2.2 of the API reference guide: http://www.ti.com/lit/ug/spru403r/spru403r.pdf).  There is no configuration interface for BCACHE, and its APIs are called explicitly by the application at runtime.

    Scott

  • 0 in reply to ScottG
    Prodigy 220 points

     

     

    Scott,

    thank you very much. I am modifying an existing project that I joined to.

    the L1/L2 caches are configured via GCONF, and I see that the map file contains their configured base addresses and sizes.

    I have added BCACHE_wbInvAll() when application starts right after bootload ( I assuem that since caches were configured, then they should be enabled at this  point - is this correct?

    my other question is whether you see a possibility that the cache can have data of older program after a new software version  is bootloaded

    regards,

     Hezi.

     

  • 0 in reply to hezi halifa
    TI__Mastermind 26780 points

    Hezi,

    Can you please post how you are configuring L1/L2 in GCONF?  I need to see that to understand what you are doing.  

    Where exactly are you calling BCACHE_wbInvAll()?  Is it in main()?  Have you made a BCACHE call (like BCACHE_setMode()) first? 

    After the bootloader is done, if you needed to do it, I would have expected just an invalidate, not a write-back and invalidate.  If the caches were disabled, then there'd be nothing to write back.

    Also, I think that the cache controller should take care of any necessary invalidation automatically as part of enabling the cache (and cache tags).  I’d need to look into the docs to verify this though.

    Can you please provide the details of how you are configuring cache, and what cache API calls you are making where?…

    Thanks,
    Scott

  • 0 in reply to ScottG
    Prodigy 220 points

     

    Hello Scott,

    thank you again for looking into it more deeply. I tried to put all relavant details:

    here is screen capture of GCONF related to cache:

    L1D cache properties:

     

    L1P cache properties:

    L2 cache properties:

     

    IRAM:

     

    DDR

     

     

    this L1p and L1D setting was performed in main of bootstrap before loading the software,  and nothing is done for L2 cache except for the GCONF setting

    // Set L1P size to 32K
        CSL_FINST(cacheRegs->L1PCFG,CACHE_L1PCFG_MODE,DISABLE);
        stall = cacheRegs->L1PCFG;

     // Set L1D size to 32K
      CSL_FINST(cacheRegs->L1DCFG,CACHE_L1DCFG_MODE,DISABLE);
        stall = cacheRegs->L1DCFG;

    from your reply, it sounds like I  need to enable cache after bootload via BCACHE calls, or would it be enabled automatically (by ti code)?

    the BCACHE_wbInvAll() that I just  added was after bootload and at some init phase before main. should I place such a call in main()

    Regards

     Hezi.

     

     

     

     

     

  • 0 in reply to hezi halifa
    TI__Mastermind 26780 points

    Hezi,

    OK, thanks.  I'll look into this and get back to you...

    Scott

  • 0 in reply to ScottG
    TI__Mastermind 26780 points

    Hezi,

    I looked at the docs and sources, and discussed with the device and bootloader teams.  My conclusion is again that you don’t need to do any writeback or invalidate after control is passed from the bootloader to your application. 

    On C6748, coming out of reset both L1P and L1D caches are enabled for their maximum sizes.  And L2 cache is disabled.  The bootloader will change the L1D cache size at some point, but right before passing control to user code, it will reconfigure L1D cache for maximum size again.  This resizing will cause an automatic writeback-invalidate of L1D by the cache controller.  So, as your program starts to run there is no need for any writeback. And really, not any need to do any invalidates either.  The L1P cache may be partially filled, but there is no need to invalidate.

    During the DSP/BIOS boot, BCACHE_setSize() will be called automatically before main() to set the sizes based upon the configuration specified on the 64PLUS tab of the “Global Settings” property page.

    So… my recommendations:

    1) Specify the cache sizes in the DSP/BIOS Global Settings properties.

    2) Don’t make any BCACHE calls to writeback or invalidate during startup.

    3) Don’t make any CSL calls for configuring/controlling cache.  Use BCACHE calls as needed for any cache coherency operations.

    Scott

  • 0 in reply to ScottG
    Prodigy 220 points

    Scott,

    thank you very much for the helpful answer.

    Hezi.