TDA4AEN-Q1: ISP migration guide from TDA4AL to TDA4AEN

Part Number: TDA4AEN-Q1
Other Parts Discussed in Thread: TDA4VL

Dear Champs,

 

My customer developed ISP SW on TDA4AL, and is trying to migrate it into TDA4AEN for new project.

Could you please check below questions from customers?

  1. Does TI foresee any functional or performance limitations when migrating ISP-related workloads from TDA4AL to TDA4EN?
  2. Given the single R5F core configuration on TDA4EN, what are TI’s recommendations or best practices for distributing workloads (e.g., offloading uGuzzi or other MCU tasks)?
  3. Are there any official migration guides, performance comparison data, or design notes between TDA4AL and TDA4EN that can be referenced?

 

Thansk and Best Regards,

SI.

  • Hi Sung-IL,

    Does TI foresee any functional or performance limitations when migrating ISP-related workloads from TDA4AL to TDA4EN?

    From the ISP H/W perspective, VPAC3L on TDA4EN is clocked up to 600MHz which is slower than the 720MHz VPAC3 on TDA4AL.
    VPAC3L has only 320KB SL2 share memory (512KB on VPAC3)
    VPAC3L also removed the (bilateral) noise filter at VPAC level and the dual-FCP support in VISS.

  • Hi  ,

    Could you please comment on these 2 questions?

    • Given the single R5F core configuration on TDA4EN, what are TI’s recommendations or best practices for distributing workloads (e.g., offloading uGuzzi or other MCU tasks)?
    • Are there any official migration guides, performance comparison data, or design notes between TDA4AL and TDA4EN that can be referenced?
  • Hi SI,

    We are not sure how much performance mGuzzi framework requires, so can't answer it. But, yes, there is a single R5F core in main domain running at (i think) 800MHz, which is lower than 1GHZ on TDA4VL, and this R5F is used for CSIRX, DSS and VPAC modules..

    Regards,

    Brijesh