AM62A7: CSI-2 RX Bandwidth Issues

Follow up on configuration systems,

port {
      csi2_cam0: endpoint {
            remote-endpoint = <&csi2rx0_in_sensor>;
            link-frequencies = /bits/ 64 <150000000>;
            clock-lanes = <0>;
            data-lanes = <1 2 3 4>;
      };
};

&csi0_port0 {
      status = "okay";

      csi2rx0_in_sensor: endpoint {
            remote-endpoint = <&csi2_cam0>;
            bus-type = <4>; /* CSI2 DPHY. */
            clock-lanes = <0>;
            data-lanes = <1 2 3 4>;
      };
};

The Linux build they're currently using seems to have "link-frequencies" not update anything, and instead the code "dead-ends" after getting pulled. i.e. The link frequency is not updating on the CSI-2 RX port. Is this normal for this part of the devicetree? Is the link-frequencies for CSI-2 updated elsewhere in the devicetree? (For reference, the customer is running a custom Yocto build).

Best,

Ryan

Hi Ryan,

I've pinged linux camera expert. There could be 1-2 days delay in their response.

Thanks,

Stan

Hi Ryan,

Our expert will Approch you meanwhile could you please try by incrementing the link-frequencies from  /bits/ 64 <150000000> to bits/ 64 <500000000>

(ie, 500 Mbps per lane)

Because,

Active data rate=height*width*bpp*fps


=1920*1080*16bits/pixel*30 ~995.33Mbps


Note:-bpp for YUV422=16.(YUV422 is 2 bytes/pixel )1 byte for Y 1byte for U/V


Raw Link Speed= Active Data Rate * (1 + Overhead)


995.3*1.25=1244.1Mbps=1.244Gbps


Note:- overhead can taken 25%

Required Per-Lane Bit Rate= Raw Link Speed/Number of Lanes


1244.1Mbps/4=311Mbps/Lane

In the DTS  set link-frequencies = /bits/ 64 <150000000>.  In the Linux kernel Device Tree for MIPI D-PHY, the link-frequencies property specifies the expected maximum bit rate per lane in Hz.

But The 150 Mbps/Lane setting is telling the D-PHY to run at less than half the speed it needs.

To ensure reliable operation and provide sufficient margin for the FPGA's clocking and the receiver's jitter tolerance, you should set the configured link frequency significantly above the required 311Mbps

A common practice is to round up to the nearest clean frequency step, or use the next 100  Mbps increment.

link-frequencies = /bits/ 64 500000000

Regards,

Dilna K

We have tried changing that node, but observed no differences on the scope.  For reference we're using the below Linux kernel version:

Linux 6.1.82-ti-ge44f83d2aa43 #1 SMP PREEMPT Mon Mar 25 23:31:33 UTC 2024 aarch64 GNU/Linux

The relevant code that extracts the link frequency is here.
drivers/media/v4l2-core/v4l2-fwnode.c:v4l2_fwnode_endpoint_alloc_parse()

The resulting data is only referenced in either i2c camera modules and then only verify a compatible frequency and an intel bridge.

Hi Jason,

Could you please check whether your sensor driver support V4L2_CID_LINK_FREQ? if the sensor driver does not implement the V4L2_CID_LINK_FREQ control, the CSI-2 RX driver fails to get the required high-speed clock rate.

and also could you please share your dmesg log and v4l2-ctl streaming command output log?

Regards,

Dilna K

You were correct.  Looking at our dummy driver we have hard-coded the V4L2_CID_LINK_FREQ to 150 MHz.  Bumping this default up to 300 MHz seem to increase fidelity of the resulting video stream.  We're looking to bump it further to 350 to hit that 3G bitrate.

Hi Jason,

Okey. Please proceed and confirm once you have successfully achieved the target bitrate.

and connect if any further assistance needed.

Regards,

Dilna K