Part Number: AM6422
Hello,
We are developing with SDK 8.6 on custom hardware. One approach involves using the FREERTOS operating system on the R5F core and utilizing the RGMII1 Ethernet peripheral of ICSSG0 without connecting a PHY chip. Instead, it is directly connected externally to an FPGA. We intend to use the FPGA to simulate a MAC and enable direct data interaction with the CPU's internal MAC. Is this approach feasible? If so, how should we proceed? We believe it is theoretically possible to bypass the PHY, but since the implementations we are using are based on PHY transceivers, we are uncertain about the specific steps. This will impact our next design decisions, and we look forward to your response.
