C6678 PCIEboot / DDR Init Issues

Zengxing,

I split this into a new thread as the question diverged from your original question.

Best Regards,

Chad

Zengxing,

For our 6678/6670 EVM, IBL is flashed into I2C EEPROM bus address 0x51. IBL provides a workaround for the PLL lockup issue (please refer to C6678 errata document, February 2011, advisory 8). For ROM boot modes (EMAC,SRIO,PCIe,Hyperlink etc) and I2C boot mode with bus address 0x50, DSP will initially boot from I2C EEPROM bus address 0x51 which does the PLL reset workaround, updates the DEVSTAT for appropriate values based on the DIP switch settings (SW3 through SW6 settings) and then re enters the ROM to accomplish the desired boot mode. Please note that the re entry is done for all boot modes except for PCIe boot mode and I2C boot mode with bus address 0x51. Below are the steps done in the IBL:

 1. FPGA samples the bootmode pins

2. FPGA forces the DSP to boot via I2C bus address 0x51

3. PLL is initialized correctly by the IBL on the I2C.

4. IBL reads the sampled bootmode from an FPGA register.

5. IBL checks the bootmode, if it is not I2C boot or it is I2C boot but with bus address 0x50, IBL writes bootmode into the DEVSTAT register

6. IBL then checks if the bootmode is PCIE boot or not. If it is, it executes some PCIE workaround to configure the PCIE registers (mainly to accept spread spectrum clock) and stays inside IBL waiting for PCIe boot.

7. If it is not PCIE boot mode, IBL writes the Boot ROM entry address into the DSP Program Counter, DSP executes the desired internal ROM boot mode or boot from I2C bus address 0x50 as normal.

 You mentioned your card has on EEPROM? Can you explain what card you are using? To make the PCIE boot code working, you need to update the IBL from MCSDK distribution.

For your question;

3.4 PCI Express (PCIe) Bootloader Operation
3.4.1 Basic Boot Operation
In the PCIe boot mode, the host configures memory and loads all the sections directly
to the memory. The bootloader configures the base address registers, the number of
windows, and their size. The PCIe power-up is configured through the external pin
PCIESSEN. PCIe boot code can configure the PCIe registers either by getting the values
from the I2C or the default values from the boot parameter table(Table 3-12).

what is the function of  boot parameter table?

Sorry, can you let me know which document you are referring to? I checked 6678 data manual (SPRS691B) and PCIE user guide (SPRUGS6A) and I didn't find the section?

Regards, Eric

Zengxing,

I found the section you mentioned in bootloader user guide (SPRUGY5A). This table configured some PCIE registers in bootrom but it will not work when using Spread Spectrum clock, so we have to reconfigure them in IBL.

Regards, Eric

I agree with Chad that you need to wait till PG version 2.0 of the silicon. To elaborate on the boot parameter table, the boot rom uses to configure the parameters of the specific boot by deriving the values from a default structure call boot parameter table. Most of the values in this structure will be default with few parameters updated by latching the boot strap pins that you set. Hope this helps.

Thanks,

Arun

1.The C6678 can always successfully hardware_set the maincore clk = 800MHZ

(by BOOTMODE[12:10]=3,Input CLK=100MHZ,PLLM=15)  every power on / off.

2.The PCIe Ref CLK is 100MHZ(LVDS,AC-coupling) on our design come from CDCE62005.  

3.On our design,the host is PPC(freescale) ,PPC can down bootloader code to the RAM of C6678  and 

   writes successfully  the boot entry address of init boot image to the magic address on core 0 too,both via PCIe.

4.We use TI_emluator connect the C6678 and can Jump the boot address to boot by CCS.

Please tell us why the C6678 can not poll the entry address? It must run the IBL for the polling? 

We can not implement that first boot IIC_EEPROM force and second boot PCIe because of no FPGA and no CPLD on our design.

So we want to know the sector about PCIe configuration of the IBL on the EEPROM.

THKs

The reason why the Shannon in you setup is not jumping to the program starting at the address specified in the boot magic address, is because of a bug in the Shannon PG1.0 silicon. The pLL for the silicon is not locking. So obviously we are not getting consistent clock to the chip. A portion of the IBL does runs the workaround to fix the PLL. If you have I2C or SPI boot mode, we can first run through this mode fix the PLL and then reenter the boot mode in PCIe. This is because in these two mode we operate with PLL bypassed. If you want to use Shannon PG1.0 then you need either a EEPROM or NOR lash connected through SPI or else as Chad mentioned, please wait for Shannon PG2.0 where we have fixed this issue.

Thanks,

Arun.

Hi,Arun

How can we assert the PLL for the silicon is not locking(you mentioned)?
----------Is only not getting consistent clock to the chip?

But we can always probe the clock of SYSCLKOUT(pin-number is AE3) which is 133MHZ(800/6)
and DDRCLKOUT(pin-number is A12/B12) which is 66.67MHZ by oscillograph every power on/off.

We guess that the IBL may do another fix for C6678 other than the PLL.
So we want to know other portion of IBL for PCIeBooTMode.

Best Regards,
John Ling

Hi John,

The problem of PLL lock is intermittent. We cannot guaranty that the PLL will generate the clock consistently. SO that is why you need this PLL fix. As for the polling, the Bootloader code does not poll the boot magic address and you need a MSI interrupt to wake up the DSP from idle. The IBL seems to run a infinite loop to monitor the boot magic address. If you don't have EEPROM, this might not help you. But in any case if you need to understand what they do, the IBL source is available in MCSDK package.

Thanks,

Arun.

Hi Arun

I understand approximately the function of IBL for C6678 PCIe boot with your great help.
I can only try to do it at the beginning of February because of the chinese Spring Festival is coming.
I will take off office from today to the end of this month.

Thanks,
John Ling

Hi Arun,

       I want to laod the IBL form JTAG then load the program from PCIE.

       How can i do? It can work?

Thanks,

zengxing