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AM6442: Regarding DDR PIN MAPPING

Ravindar A
Prodigy 20 points

Part Number: AM6442

Hi,

We are using AM6442 processor based AM64X EVM using RT LINUX development.

I wanted to know, where can we find the DDR(MT40A1G16KD-062EIT:E ) pin configuration in UBOOT for existing EVM board?

I mean which signals connected to HW pin, for other pheripherals we can able to see in related DTS file and able to modifu/add.

 

Thanks,

Ravindar

 

 

  • 0
    TI__Guru* 95821 points

    There is no pin configuration for the DDR interface.  These are dedicated pins used by the DDR PHY and are not modifiable

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 125 points

    Hi,

    I our AM6442 Processor custom board, we wanted to use DDR4 (MT40A1G16TB-062E IT:F ) new part.

    In that we wanted to change the AM6442 pins connected with DDR4 Highlighted below in Custom Board Signal Column.

    How to proceed for the custom board what things need to be modify in TI RT-Linux SDK to connect with new DDR4 Module?

    As mentioned above: There is no pin configuration for the DDR interface

    Wanted to know how exactly DDR4 FW driver communicating with HW Pins of AM6442 Processor?

    Thanks,

    Ravindar

    PIn Number PIn Name Reference Voltage EVM Signal Name Custom Board Signal Name Custom Board Interface Custom Board I/O/B/P Remarks
    H2 DDR0_ACT_N VDDS_DDR, VDDS_DDR_C DDR_ACTn DDR_ACTn DDR4 O
    H1 DDR0_ALERT_N VDDS_DDR, VDDS_DDR_C DDR_ALERTn DDR_ALERTn DDR4 IO
    J5 DDR0_CAS_N VDDS_DDR, VDDS_DDR_C DDR_A15_CAS DDR_A15_CAS DDR4 O
    K5 DDR0_PAR VDDS_DDR, VDDS_DDR_C DDR_PARITY DDR_PARITY DDR4 O
    F6 DDR0_RAS_N VDDS_DDR, VDDS_DDR_C DDR_A16_RAS DDR_A16_RAS DDR4 O
    H4 DDR0_WE_N VDDS_DDR, VDDS_DDR_C DDR_A14_WEn DDR_A14_WEn DDR4 O
    D2 DDR0_A0 VDDS_DDR, VDDS_DDR_C DDR_A0 DDR_A0 DDR4 O
    C5 DDR0_A1 VDDS_DDR, VDDS_DDR_C DDR_A1 DDR_A1 DDR4 O
    E2 DDR0_A2 VDDS_DDR, VDDS_DDR_C DDR_A2 DDR_A2 DDR4 O
    D4 DDR0_A3 VDDS_DDR, VDDS_DDR_C DDR_A3 DDR_A3 DDR4 O
    D3 DDR0_A4 VDDS_DDR, VDDS_DDR_C DDR_A4 DDR_A4 DDR4 O
    F2 DDR0_A5 VDDS_DDR, VDDS_DDR_C DDR_A5 DDR_A5 DDR4 O
    J2 DDR0_A6 VDDS_DDR, VDDS_DDR_C DDR_A6 DDR_A6 DDR4 O
    L5 DDR0_A7 VDDS_DDR, VDDS_DDR_C DDR_A7 DDR_A7 DDR4 O
    J3 DDR0_A8 VDDS_DDR, VDDS_DDR_C DDR_A8 DDR_A8 DDR4 O
    J4 DDR0_A9 VDDS_DDR, VDDS_DDR_C DDR_A9 DDR_A9 DDR4 O
    K3 DDR0_A10 VDDS_DDR, VDDS_DDR_C DDR_A10 DDR_A10 DDR4 O
    J1 DDR0_A11 VDDS_DDR, VDDS_DDR_C DDR_A11 DDR_A11 DDR4 O
    M5 DDR0_A12 VDDS_DDR, VDDS_DDR_C DDR_A12 DDR_A12 DDR4 O
    K4 DDR0_A13 VDDS_DDR, VDDS_DDR_C DDR_A13 DDR_A13 DDR4 O
    G4 DDR0_BA0 VDDS_DDR, VDDS_DDR_C DDR_BA0 DDR_BA0 DDR4 O
    G5 DDR0_BA1 VDDS_DDR, VDDS_DDR_C DDR_BA1 DDR_BA1 DDR4 O
    G2 DDR0_BG0 VDDS_DDR, VDDS_DDR_C DDR_BG0 DDR_BG0 DDR4 O
    H3 DDR0_BG1 VDDS_DDR, VDDS_DDR_C TP59(DNI) O
    H5 DDR0_CAL0 VDDS_DDR, VDDS_DDR_C 240Ohm to GND 240Ohm to GND DDR4 A
    F1 DDR0_CK0 VDDS_DDR, VDDS_DDR_C DDR_CLKP DDR_CLKP DDR4 O
    E1 DDR0_CK0_N VDDS_DDR, VDDS_DDR_C DDR_CLKN DDR_CLKN DDR4 O
    F4 DDR0_CKE0 VDDS_DDR, VDDS_DDR_C DDR_CKE DDR_CKE DDR4 O
    F3 DDR0_CKE1 VDDS_DDR, VDDS_DDR_C TP58(DNI) O
    E3 DDR0_CS0_N VDDS_DDR, VDDS_DDR_C DDR_CSn DDR_CSn DDR4 O
    E4 DDR0_CS1_N VDDS_DDR, VDDS_DDR_C TP60(DNI) O
    B2 DDR0_DM0 VDDS_DDR, VDDS_DDR_C DDR_LDM DDR_LDM DDR4 IO
    M2 DDR0_DM1 VDDS_DDR, VDDS_DDR_C DDR_UDM DDR_UDM DDR4 IO
    A3 DDR0_DQ0 VDDS_DDR, VDDS_DDR_C DDR_DQ0 DDR_DQ0 DDR4 IO
    A2 DDR0_DQ1 VDDS_DDR, VDDS_DDR_C DDR_DQ5 DDR_DQ6 DDR4 IO
    B5 DDR0_DQ2 VDDS_DDR, VDDS_DDR_C DDR_DQ4 DDR_DQ3 DDR4 IO
    A4 DDR0_DQ3 VDDS_DDR, VDDS_DDR_C DDR_DQ1 DDR_DQ5 DDR4 IO
    B3 DDR0_DQ4 VDDS_DDR, VDDS_DDR_C DDR_DQ3 DDR_DQ2 DDR4 IO
    C4 DDR0_DQ5 VDDS_DDR, VDDS_DDR_C DDR_DQ6 DDR_DQ1 DDR4 IO
    C2 DDR0_DQ6 VDDS_DDR, VDDS_DDR_C DDR_DQ7 DDR_DQ4 DDR4 IO
    B4 DDR0_DQ7 VDDS_DDR, VDDS_DDR_C DDR_DQ2 DDR_DQ7 DDR4 IO
    N5 DDR0_DQ8 VDDS_DDR, VDDS_DDR_C DDR_DQ8 DDR_DQ8 DDR4 IO
    L4 DDR0_DQ9 VDDS_DDR, VDDS_DDR_C DDR_DQ15 DDR_DQ15 DDR4 IO
    L2 DDR0_DQ10 VDDS_DDR, VDDS_DDR_C DDR_DQ14 DDR_DQ12 DDR4 IO
    M3 DDR0_DQ11 VDDS_DDR, VDDS_DDR_C DDR_DQ10 DDR_DQ10 DDR4 IO
    N4 DDR0_DQ12 VDDS_DDR, VDDS_DDR_C DDR_DQ9 DDR_DQ11 DDR4 IO
    N3 DDR0_DQ13 VDDS_DDR, VDDS_DDR_C DDR_DQ12 DDR_DQ13 DDR4 IO
    M4 DDR0_DQ14 VDDS_DDR, VDDS_DDR_C DDR_DQ11 DDR_DQ14 DDR4 IO
    N2 DDR0_DQ15 VDDS_DDR, VDDS_DDR_C DDR_DQ13 DDR_DQ9 DDR4 IO
    C1 DDR0_DQS0 VDDS_DDR, VDDS_DDR_C DDR_LDQS_P DDR_LDQS_P DDR4 IO
    B1 DDR0_DQS0_N VDDS_DDR, VDDS_DDR_C DDR_LDQS_N DDR_LDQS_N DDR4 IO
    N1 DDR0_DQS1 VDDS_DDR, VDDS_DDR_C DDR_UDQS_P DDR_UDQS_P DDR4 IO
    M1 DDR0_DQS1_N VDDS_DDR, VDDS_DDR_C DDR_UDQS_N DDR_UDQS_N DDR4 IO
    E5 DDR0_ODT0 VDDS_DDR, VDDS_DDR_C DDR_ODT DDR_ODT DDR4 O
    F5 DDR0_ODT1 VDDS_DDR, VDDS_DDR_C TP62(DNI) O
    D5 DDR0_RESET0_N VDDS_DDR, VDDS_DDR_C DDR_RESET# DDR_RESET# DDR4 O
  • 0 in reply to Avothu Ravindar
    TI__Guru* 95821 points

    DDR DQ signals can be freely swapped within a byte.  Please see https://www.ti.com/lit/pdf/spracu1 for more information on DDR layout guidelines.  

    Also for software drivers, please consult the DDR register configuration tool here:  https://dev.ti.com/sysconfig/?product=Processor_DDR_Config&device=AM64x

    Instructions are in the README link in the tool.  The Micron device you chose is very close to the one on the AM64x EVM, so i would start with the configuration for that board.  The only other changes that may need to be may are for termination and drive strength, based on your board design and simulations.

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 125 points

    Ok Thanks