Part Number: DRA829V
Other Parts Discussed in Thread: DRA829, INA226
Dear experts,
I have applied the patch from www.ti.com/.../sdaa069.pdf for DRA829 and I have some questions. The only change to the patch is clocks parameter for the cpus.
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At first glance it looks like cpufreq subsystem is working with the OPP but verifying frequency with k3conf shows no changes to actual cpu frequency. If I set the ondemand governor both cpuinfo_cur_freq and scaling_cur_freq show 250 MHz but k3conf dump processor show 2GHz.
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The thermal subsystem (cpu as passive cooling device) does change cpu frequency verified with k3conf but temperature, power consumption and performance doesn't change. I set the alert trip point to 35 degC so cpu is set to 250 MHz (verified with k3conf) and I still get same performance in coremark and stress-ng benchmarks as at 2 GHz. Our idle cpu temperature is around 48 degC and during benchmark/stress test temperature increases to ~52 degC.
The diff for dra829:
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi
index 927f7614ae7a..7b308c18f148 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi
@@ -26,12 +26,25 @@ mpu_thermal: mpu-thermal {
thermal-sensors = <&wkup_vtm0 1>;
trips {
+ mpu_alert: mpu-alert {
+ temperature = <65000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "passive";
+ };
+
mpu_crit: mpu-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
+
+ cpu_cooling_maps: cooling-maps {
+ map0 {
+ trip = <&mpu_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
c7x_thermal: c7x-thermal {
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index 5a72c518ceb6..e2acce5cda42 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -48,6 +48,10 @@ cpu0: cpu@0 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_0>;
+ clocks = <&k3_clks 202 2>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
};
cpu1: cpu@1 {
@@ -62,9 +66,40 @@ cpu1: cpu@1 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_0>;
+ clocks = <&k3_clks 203 0>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
};
};
+ cpu0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp6-2000000000 {
+ opp-hz = /bits/ 64 <2000000000>;
+ clock-latency-ns = <300000>;
+ };
+
+ opp4-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ clock-latency-ns = <300000>;
+ };
+
+ opp2-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ clock-latency-ns = <300000>;
+ };
+
+ opp1-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ clock-latency-ns = <300000>;
+ };
+ };
+
+
+
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;Best regards,
Oliver Talevski
