Part Number: AM62L
Hello.
We have connected MRAM to the OSPI(as Quad-SPI) of the AM62L and are measuring the read and write performance.
The PSDK is using version 11.00.15.05.
I am checking how much the performance improves when changing the OSPI clock frequency(OSPI_CLK) to 25MHz, 50MHz, and 100MHz.
When performing a 512KB full area read using the dd command, the read time decreases proportionally with the frequency.(25MHz: 43ms, 50MHz: 20ms, 100MHz: 8ms)
However, in the case of writing, the writing time becomes slightly shorter according to the frequency, but it is not as short as the read time. (25MHz: 127ms, 50MHz: 104ms, 100MHz: 98ms)
Looking at the waveform during writing, the write operation is performed in blocks of 1 block (256 Bytes) each, and there is a waiting time where CS is deasserted after each write completion.
When looking at the writing time per block, it decreases in proportion to the frequency.
On the other hand, the waiting time while CS is deasserted does not shorten in proportion to the frequency.
It is considered that the write time has not been shortened by this waiting time.
What is this waiting time during deassertion waiting for?
And is it possible to reduce this waiting time?
Additionally, the cdns,tshsl-ns time set in the device tree is on the order of nanoseconds, which is considered not to be dominant.
Best Regards,
Takayuki
