This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Right Formula for C674x I2C Clock Calculation?

Hi,

According to C6745/C6747 TRM(spruh91A) page-920, ICCL/ICCH clock low/high-time divide-down value is 1-65536 in the descriptions in table 22-8 and 22-9 .
So, is the right formula to calculate I2C serial clock frequency below?

                                   prescaled module clock frequency
  I2C serial clock = ------------------------------------------------
                                        (ICCl + 1 + d) + (ICCH + 1 +d)
                                                  ~~~                       ~~~

Thanks in advance for your cooperation.

Best regards,
j-breeze 

  • Yes that is correct.

    Jeff

  • Hi jeff-san,

    Thank you for your prompt reply.
    You mentioned that the formula in the document(spruh91a) was not correct, however I'd like to ask you a question again.

    I found a sample code for C6747 I2C0 in the QuickStartOMAPL1x rCSL.
    The code use the fomula in the doc(spruh91a).

    Please refer IPSC, ICCL and ICCH values below in thecode for I2C clock setting.   

    -----------------------------------------------
    o Sample Code Source File Name 
    -----------------------------------------------

    <Installed DIR>\quickStartOMAPL1x_rCSL\OMAPL1x\rCSL_examples\evmOMAPL137\DSP_examples\i2c\I2C_eeprom_dspL137\src\main.c

    ----------------------------------------------
    o I2C Setup Code (Line 108~136)
    ----------------------------------------------

    static void setup_I2C0 (void)
    {
        // Place I2C in Reset
        CSL_FINST(i2c0Regs->ICMDR, I2C_ICMDR_IRS, DISABLE);
       
        // Configure I2C Mode (Select 7-Bit Addressing & Transfer 8 Bits)
        CSL_FINST(i2c0Regs->ICMDR, I2C_ICMDR_XA, 7BIT);
        CSL_FINST(i2c0Regs->ICMDR, I2C_ICMDR_BC, 8BIT);
       
        // Disable Other I2C Modes (Repeat, Loopback, Free Data, Start Byte)
        CSL_FINST(i2c0Regs->ICMDR, I2C_ICMDR_RM, DISABLE);
        CSL_FINST(i2c0Regs->ICMDR, I2C_ICMDR_DLB, DISABLE);
        CSL_FINST(i2c0Regs->ICMDR, I2C_ICMDR_FDF, DISABLE);
        CSL_FINST(i2c0Regs->ICMDR, I2C_ICMDR_STB, DISABLE);
       
        // Configure I2C Clock Operation Freq (MUST BE BETWEEN 6.7 AND 13.3 MHz)
        CSL_FINS(i2c0Regs->ICPSC, I2C_ICPSC_IPSC, DIVto12MHZ);
       
        // Configure Clock Low/High Time (20 kHz)
        CSL_FINS(i2c0Regs->ICCLKL, I2C_ICCLKL_ICCL, 294);
        CSL_FINS(i2c0Regs->ICCLKH, I2C_ICCLKH_ICCH, 294);
       
        // Disable and Clear Pending I2C Interrupts
        i2c0Regs->ICIMR = CSL_I2C_ICIMR_RESETVAL;
        i2c0Regs->ICSTR = i2c0Regs->ICSTR;
       
        // Remove I2C from Reset
        CSL_FINST(i2c0Regs->ICMDR, I2C_ICMDR_IRS, ENABLE);
    }/* setup_I2C0 */

    -----------------------------------------------------------
    o I2C clock calculation from the aboce code
    -----------------------------------------------------------

    I2C0 input clock frequency = AUXCLK = 24MHz 

    IPSC = DIVto12MHZ = 1

                                                                       I2C0 input clock frequency     24MHz
    Prescaled module clock frequency = ------------------------------------ = ---------- = 12MHz
                                                                                     (IPSC + 1)                     (1 + 1)

    d = 6 (IPSC = 1)
    ICCL = 294
    ICCH = 294

                                                       Prescaled module clock frequency                12Mhz
    I2C serial clock frequency = ----------------------------------------------- = ---------------------------- = 20kHz
                                                                 (ICCL + d) + (ICCH + d)               (294 + 6) + (294 + 6)

    So, if you'll excuse me, could you please check it again which formula is correct?
    Thank you very much in advance.

    Best regards,
    j-breeze 

  • Sorry about that. Even though the ICCL/ICCH registers are programmed to be value - 1 (ie 0 = /1, 0xFFFF = /65535), that is compensated for by the "d" values in the formula. So no, you do not need to do a +1 again assuming you use the correct "d" values shown.

    Jeff

  • Jeff-san,

    I got it.
    Thank you for your support and the link info.

    Best regards,
    j-breeze