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MSI support on TMS320C667X

Mark Swick
Intellectual 565 points
Other Parts Discussed in Thread: TMS320C6672

Hello,

Hello,

We are planning to interface and Integra ARM (RC) to a TMS320C6672 (EP) across the PCIe. The DSP EP is also interfacing to a FPGA (EP). We are planning on using SYS BIOS. How much Hwi interrupt support is provided for MSI?

 I am assuming I need to design the interrupt generation from the DSP to the RC and come up with a scheme for generating MSIs from the ARM RC to the DSP EP. His scheme will also need to support generation of MSIs in the FPGA EP directed toward the DSP EP.

Does the Hwi interface API support registering ISRs, enabling, disabling, and resolving MSI interrupts? Where is this documented?

How much MSI support do I need to code myself?

Mark

  • 0
    TI__Genius 12065 points

    Mark,

    Based on the PCIe standard specification, only the MSI generation from EP to RC is supported. RC will receive the MSI interrupt but should not generate it to EP.

    But if your customized design does not need to be compatible with the PCIe standard spec, you could generate MSI interrupt from RC to EP (C667x PCIe) or EP to EP (C667x PCIe), since the PCIe module in C667x devices supports the additional capability.

    For the MSI generation from C667x PCIe (EP) to RC, please refer to the description in section 2.13.2.2 in the PCIe user's guide. It is the standard scheme for MSI from EP to RC.

    For the MSI generation from RC to C667x PCIe (EP) or from FPGA (EP) to C667x PCIe (EP), please refer to the description in section 2.13.3 and 2.13.4 in PCIe user's guide. The RC or other EP could write to the MSI_IRQ register in the C667x PCIe to generate the MSI interrupt in C667x.

    Regarding to the HWI support in SYS/BIOS, there are some materials within TI, like TI SYS/BIOS Real-time Operating System v6.x User's Guide and C6000 Embedded Design Workshop Using BIOS page, describing the APIs. 

    If you would like to program the MSI generation/reception yourself (or even use SYS/BIOS HWI), please refer to the PCIe user's guide and also the C66x CorePac user's guide. We need to enable CPU (DSP CorePac) interrupt controller to accept the PCIe MSI interrupt in C66x. Also please refer to section 7.9 in the C66x data manual for the MSI event number going to be used in your code or HWI configuration.

    Sincerely,

    Steven

  • 0 in reply to Steven Ji
    Intellectual 565 points

    Steven,

    Thanks for the response. I have a few more questions.

    Looking at the documents you pointed me too, it looks like all incoming MSIs are mapped to event 17. To resolve which MSI is active I would need to read the MSIn (n = 0-7) Interrupt Raw Status register.

    1. Do I need to do anything to clear the interrupt status in this register? Do we use MSI 0 Interrupt Enabled Status Register (MSI0_IRQ_STATUS) register to clear these bits. There is a conflict in the Figure 3-24 legend indicate bits are cleared by writing a 1, and Table 3-25 where the the description of Table indicates bits are cleared by writing a 0.
    2. If I were to enable MSI vectors 24, 16, 8, and 0, are there any potential race conditions that would cause me to miss an interrupt?
    3. My FPGA can generate 80 or more unique events. Can I use the General Purpose Registers (GPR0-GPR3) to help resolve unique events?

     I am assuming the interrupt enable clear and set registers are used to enable and disable the interrupts.

  • 0 in reply to Mark Swick
    TI__Genius 12065 points

    Mark,

    1. You need to clear the interrupt status bit(s) in MSIn_IRQ_STATUS register before accepting the next interrupt. There is one typo in figure 3-25 (and other MSIn_IRQ_STATUS registers). So it should be to clear the bits by writing a 1 (one), not 0. It should be corrected in the next release.

    2. It should be no problem to receive multiple MSI interrupts (with different MSI vectors) at the same time. But it may be the situation that the new interrupt is coming while you are clearing the same bit in the register. So when you plan to clear those flags in the status register, please make sure to disable the interrupt first before accessing the MSI0_ISR_STATUS register. Then re-enable the interrupt after clearing the status. 

    3. The GPRn registers could be used by the user for generic/additional information. It should be no issue to use them along with the MSI interrupts.

    You assumption is correct that the MSIn_IRQ_ENABLE_SET register is to ENABLE and MSIn_IRQ_ENABLE_CLR register is to DISABLE the interrupts.

    Sincerely,

    Steven