AM69: U-Boot SPL USB DFU: cdns3 occasionally fails to pull up D+ in cdns3_gadget_config

Renan Santos Adriano

Part Number: AM69

Hello Experts,

To flash our AM69 modules, we enter recovery mode and use DFU provided by the boot ROM to flash the U-Boot SPL on the R5 core of the SoC (tiboot3.bin built by U-Boot).

This part consistently works.

Then, the SPL runs on the R5 core and in turn starts a USB gadget providing DFU. This works most of the time, but not always. Sometimes, we observe that our gadget is never detected by the attached PC.

Debugging shows that in these cases the D+ line is never pulled up by the SoC, and therefore an attached PC will never see the gadget come up and will never try to enumerate this new USB device.

To me, it smells like a bug in cdns3 that is only triggered in certain conditions, but I have not yet figured out which conditions. This form post reports a bug that sounds like it might have a similar root cause: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1503411/am6442-usb-device-configure-cause-linux-system-hang-2

Because of the similarities, I have tried some of the same patches to the cdns3 driver.
- Removed `writel(PUSB_PWR_FST_REG_ACCESS, &priv_dev->regs->usb_pwr);` from `cdns3_gadget_config`. Bug still occurred.
- Changed USB config in device tree to super-speed and usb3 IP instead of usb2 IP. Bu still occurred.

I have also written to the USB Config register (0x6020000) from `armv7/start.S` to test the behaviour of activating the D+ pullup as the first thing we do after reset. In this case, the pullup is always set correctly and the bug does not occur.

Further debugging showed the sporadic failure of setting the pullup occurs only after the following lines in `drivers/usb/cdns3/gadget.c:cdns3_gadget_udc_start()`:
```
cdns3_gadget_udc_set_speed(gadget, gadget->max_speed);
cdns3_gadget_config(priv_dev);
```

The call to `cdns3_gadget_config` includes setting the pullup at the end, which fails sometimes. It seems that the configuration that happened in these steps can bring the cdns3 IP into a state where sometimes, writing USB_CONF_DEVEN (bit 14) to the USB Config register, has no effect.

When in this broken condition and we attach GDB at that point, I cannot manually write to the USB config register to try and activate the pullup either. I've tried to write USB_CONF_DEVDS (device disable) and then write device enable, but no luck there.

Interestingly, I see that each time the gadget comes up successfully (i.e.: pullup on D+ was asserted), the status register of USB0 reads out `0x10124630`. When it failed, the register reads `0x101e4640`.

I added the following infinite loop right after `cdns3_gadget_config` in `cdns3_gadget_udc_start`:
```
static u32 prev_status_reg;

while (1) {

u32 status_reg = readl(0x6020004);

if (status_reg != prev_status_reg)

printf("status_reg: %x\n", status_reg);

prev_status_reg = status_reg;

}
```

This gives me an overview of how the status register changes after the config call, and a place to hook into with GDB to play around. Below is the output of first a working run (pullup enabled), and then a broken run (pullup never enabled). You can see that the status register always starts off the same, but evolves when things are working, and stops changing at `0x101e4640` when they don't.

```
U-Boot SPL 2024.04-00807-gd7915930c05d-dirty (Nov 12 2025 - 09:48:22 +0100)

SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
HW CFG: 0x00
Initialized 4 DRAM controllers
SPL initial stack usage: 13456 bytes
Trying to boot from DFU
spl_ram_load_image called
run_usb_dnl_gadget called
status_reg: 101c4640
status_reg: 101e4640
status_reg: 10124620
status_reg: 101a4620
status_reg: 10124620
status_reg: 10124630

U-Boot SPL 2024.04-00807-gd7915930c05d-dirty (Nov 12 2025 - 09:48:22 +0100)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
HW CFG: 0x00
Initialized 4 DRAM controllers
SPL initial stack usage: 13456 bytes
Trying to boot from DFU
spl_ram_load_image called
run_usb_dnl_gadget called
status_reg: 101c4640
status_reg: 101e4640
```

So according to this status register (0x6020004), this USB always starts of in SuperSpeed mode (I have verified that changing the settings in the Device Tree to high-speed or full-speed does not affect this) and then changes to Full-Speed/High-Speed afterwards.

Since that change does not happen in the broken case, it seems to me that there is some bug in the hardware there or in the software support.

My debugging took place on U-Boot v2024.04 but I have looked at and tested the changes in cdns3 upstream, there don't seem to be many.

Any guidance on this issue?

Kind regards and thanks for reading,

Ernest Van Hoecke - Toradex

1 month ago

0 Ernest Van Hoecke 1 month ago

Prodigy 110 points

Renan Santos Adriano said:
Further debugging showed the sporadic failure of setting the pullup occurs only after the following lines in `drivers/usb/cdns3/gadget.c:cdns3_gadget_udc_start()`:
```
cdns3_gadget_udc_set_speed(gadget, gadget->max_speed);
cdns3_gadget_config(priv_dev);
```

Further testing showed that I was wrong here, it seems like the issue can also occur before this point. It's my gut feeling that at some places it gets more likely to happen but it's hard to gather accurate statistics for now. Will keep looking.

0 Ernest Van Hoecke 1 month ago

Prodigy 110 points

Renan Santos Adriano said:
- Changed USB config in device tree to super-speed and usb3 IP instead of usb2 IP. Bu still occurred.

So I did more (statistical) testing here and have some interesting results. When I change the device tree to have usb0 use USB SuperSpeed, the bug occurs less often than when I change it to only use USB2, but it does not disappear. I had a script compare both binaries and here is the result:

```
Good SS runs: 1051
Good USB2 runs: 999
Bad SS runs: 27
Bad USB2 runs: 80

```

When I first tried this test, I ran it with binaries that still included a lot of my debug code (various statistics and prints), and the bug occurred much less often:

```
Good SS runs: 6650
Good USB2 runs: 6526
Bad SS runs: 9
Bad USB2 runs: 135

```

To me this all seems like something strange timing/hardware related is going on.

Kind regards,

Ernest

0 Ernest Van Hoecke 17 days ago

Prodigy 110 points

In my last test I still had some debugging and logging options enabled, so I repeated the SuperSpeed vs USB2 test again with a cleaner setup and for a longer time. The results are below:

```

Good SS runs: 23526
Good USB2 runs: 22211
Bad SS runs: 30
Bad USB2 runs: 1346

```

The difference between them is clearly huge, and yet configuring the USB as SuperSpeed does not fully solve the issue. I'll park this issue on my side, any input is certainly appreciated, thanks!

0 Ernest Van Hoecke 14 days ago

Prodigy 110 points

Strangely, enabling SuperSpeed only really improves these statistics if I also disable `pcie0` in the Device Tree. That is weird because with our device tree, the serdes lanes are separate and not shared between the pcie0 and usb0 nodes, so I do not understand why pcie0 being enabled or disabled in the SPL would have any impact.

Our serdes config in the base DTSI:

/* Aquila PCIE_1 */
&pcie0_rc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0_reset>;
	num-lanes = <2>;
	phy-names = "pcie-phy";
	phys = <&serdes1_pcie0_2l_link>;
	reset-gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>;
	status = "disabled";
};

&usb0 {
	phys = <&serdes0_usb0_ss_link>;
	phy-names = "cdns3,usb3-phy";
	dr_mode = "otg";
	maximum-speed = "super-speed";
	usb-role-switch;
	status = "disabled";
};

&usb_serdes_mux {
	idle-states = <0>; /* USB0 to SERDES lane 3 */
};


&serdes0 {
	status = "okay";

	/* Aquila PCIE_2 */
	serdes0_pcie1_2l_link: phy@0 {
		reg = <0>;
		#phy-cells = <0>;
		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
		cdns,num-lanes = <2>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
	};

	/* On-module PCIe Wi-Fi */
	serdes0_pcie3_1l_link: phy@2 {
		reg = <2>;
		#phy-cells = <0>;
		resets = <&serdes_wiz0 3>;
		cdns,num-lanes = <1>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
	};

	/* Aquila USB0 SS */
	serdes0_usb0_ss_link: phy@3 {
		reg = <3>;
		#phy-cells = <0>;
		resets = <&serdes_wiz0 4>;
		cdns,num-lanes = <1>;
		cdns,phy-type = <PHY_TYPE_USB3>;
	};
};

&serdes1 {
	status = "okay";

	/* Aquila PCIE_1 */
	serdes1_pcie0_2l_link: phy@0 {
		reg = <0>;
		#phy-cells = <0>;
		resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
		cdns,num-lanes = <2>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
	};

	/* On-module PCIe USB Bridge */
	serdes1_pcie2_1l_link: phy@2 {
		reg = <2>;
		#phy-cells = <0>;
		resets = <&serdes_wiz1 3>;
		cdns,num-lanes = <1>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
	};
};

&serdes_ln_ctrl {
	idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,     /* Aquila PCIE_2 L0          */
		      <J784S4_SERDES0_LANE1_PCIE1_LANE1>,     /* Aquila PCIE_2 L1          */
		      <J784S4_SERDES0_LANE2_PCIE3_LANE0>,     /* On-module PCIe Wi-Fi      */
		      <J784S4_SERDES0_LANE3_USB>,             /* Aquila USB0 SS            */
		      <J784S4_SERDES1_LANE0_PCIE0_LANE0>,     /* Aquila PCIE_1 L0          */
		      <J784S4_SERDES1_LANE1_PCIE0_LANE1>,     /* Aquila PCIE_1 L1          */
		      <J784S4_SERDES1_LANE2_PCIE2_LANE0>,     /* On-module PCIe USB Bridge */
		      <J784S4_SERDES1_LANE3_QSGMII_LANE2>,    /* Aquila SGMII MSP_9        */
		      <J784S4_SERDES2_LANE0_QSGMII_LANE5>,    /* Aquila SGMII MSP_6        */
		      <J784S4_SERDES2_LANE1_QSGMII_LANE6>,    /* Aquila SGMII MSP_7        */
		      <J784S4_SERDES2_LANE2_QSGMII_LANE7>,    /* Aquila SGMII MSP_8        */
		      <J784S4_SERDES2_LANE3_QSGMII_LANE8>,    /* Aquila ETH_2 xGMII        */
		      <J784S4_SERDES4_LANE0_EDP_LANE0>,       /* Aquila DP L0              */
		      <J784S4_SERDES4_LANE1_EDP_LANE1>,       /* Aquila DP L1              */
		      <J784S4_SERDES4_LANE2_EDP_LANE2>,       /* Aquila DP L2              */
		      <J784S4_SERDES4_LANE3_EDP_LANE3>;       /* Aquila DP L3              */
};

&serdes_refclk {
	clock-frequency = <100000000>;
	status = "okay";
};

&serdes_wiz0 {
	status = "okay";
};

&serdes_wiz1 {
	status = "okay";
};

&serdes_wiz2 {
	status = "disabled";
};

&serdes_wiz4 {
	status = "disabled";
};

Our patch to u-boot.dtsi that enables super-speed:

diff --git a/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi b/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi
index 09cd7a78808b..9f30b1be5c90 100644
--- a/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi
+++ b/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi
@@ -121,6 +121,10 @@
        bootph-pre-ram;
 };
 
+&pcie0_rc {
+       status = "disabled";
+};
+
 &pinctrl_main_uart8 {
        bootph-pre-ram;
 };
@@ -137,6 +141,14 @@
        bootph-pre-ram;
 };
 
+&serdes0 {
+       boothph-pre-ram;
+};
+
+&serdes0_usb0_ss_link {
+       boothph-pre-ram;
+};
+
 &sms {
        bootph-pre-ram;
        k3_sysreset: sysreset-controller {
@@ -146,15 +158,12 @@
 };
 
 &usb0 {
-       /delete-property/ phys;
-       /delete-property/ phy-names;
        dr_mode = "peripheral";
-       maximum-speed = "high-speed";
+       maximum-speed = "super-speed";
        bootph-pre-ram;
 };
 
 &usbss0 {
-       ti,usb2-only;
        bootph-pre-ram;
 };

We would like to understand why I need to disable the `pcie0_rc` node in this patch to really have an impact.

For reference, the idea to switch to SuperSpeed came from here: AM6442: USB device configure cause Linux system hang (2)

Do you have any guidance here?

Regards,
Ernest

0 Gokul Praveen 12 days ago in reply to Ernest Van Hoecke

TI__Genius 14400 points

HI Ernest,

Really sorry for the delayed response, Ernest.

So basically, only 2 IPs can be used on a particular serdes which is a hardware limitation.
Currently, I believe, on serdes 0 , you are using PCIE1, PCIE3 and USB. So you will have to disable either PCIE3 or PCIE1. A better option would be to change <J784S4_SERDES0_LANE2_PCIE3_LANE0> to <J784S4_SERDES0_LANE2_IP3_UNUSED> and remove the below section from serdes 0:
Similar is the case for Serdes1 as well where PCIE0, PCIE2 and QSGMII is used. You can change <J784S4_SERDES1_LANE3_QSGMII_LANE2> to <J784S4_SERDES1_LANE3_IP4_UNUSED> as well as remove that QSGMII serdes link section , if used inside serdes 1 device tree node.

Can you give a try with these configuration, if possible, Ernest.

Best Regards

Gokul Praveen

0 Ernest Van Hoecke 9 days ago in reply to Gokul Praveen

Prodigy 110 points

Hi Gokul,

Thanks for your input.

After further testing I can confirm that with only 2 IPs per SerDes, I no longer need to disable pcie0 to drastically reduce the rate of occurrence of this issue, but it is still not fully solved. Below are my results from running your configuration over the weekend, compared to the default with no changes to the SerDes configuration and pcie0 still enabled:

```
Good default runs: 33105
Good SerDes-fixed runs: 34057
Bad default runs: 1048
Bad SerDes-fixed runs: 96
```

The 96 in 34153 approaches a rate that might be acceptable, but I am worried the real problem is still hidden since this occurrence is actually a little higher than with past tests I posted in this thread where I disabled pcie0. Though I don't want to compare too heavily since the statistics are very close and those tests were run some time apart.

We were under the impression that the limit on the SerDes was 2 protocols, not 2 IPs.

Kind regards,

Ernest

0 Gokul Praveen 9 days ago in reply to Ernest Van Hoecke

TI__Genius 14400 points

Hi Ernest,

Even I am a little bit skeptical on the root cause of this issue.

Can you ensure that the SW2 settings are in UFP (upstream facing port)mode.

Also can you try adding the below patch:

diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
index 9eaf7e40ab6..570467278c8 100644
--- a/drivers/usb/cdns3/gadget.c
+++ b/drivers/usb/cdns3/gadget.c
@@ -1027,7 +1027,7 @@ void cdns3_set_hw_configuration(struct cdns3_device *priv_dev)
 	if (priv_dev->hw_configured_flag)
 		return;

-	writel(USB_CONF_CFGSET, &priv_dev->regs->usb_conf);
+	cdns3_set_register_bit(&priv_dev->regs->usb_conf, USB_CONF_CFGSET);
 	writel(EP_CMD_ERDY | EP_CMD_REQ_CMPL, &priv_dev->regs->ep_cmd);

 	cdns3_set_register_bit(&priv_dev->regs->usb_conf,
@@ -1535,7 +1535,7 @@ void cdns3_configure_dmult(struct cdns3_device *priv_dev,

 	/* For dev_ver > DEV_VER_V2 DMULT is configured per endpoint */
 	if (priv_dev->dev_ver <= DEV_VER_V2)
-		writel(USB_CONF_DMULT, &regs->usb_conf);
+		cdns3_set_register_bit(&regs->usb_conf, USB_CONF_DMULT);

 	if (priv_dev->dev_ver == DEV_VER_V2)
 		writel(USB_CONF2_EN_TDL_TRB, &regs->usb_conf2);
@@ -2268,7 +2268,7 @@ int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev)
 		return 0;

 	/* Start driving resume signaling to indicate remote wakeup. */
-	writel(USB_CONF_LGO_L0, &priv_dev->regs->usb_conf);
+	cdns3_set_register_bit(&priv_dev->regs->usb_conf, USB_CONF_LGO_L0);

 	return 0;
 }
@@ -2344,7 +2344,7 @@ static void cdns3_gadget_config(struct cdns3_device *priv_dev)

 	/* enable generic interrupt*/
 	writel(USB_IEN_INIT, &regs->usb_ien);
-	writel(USB_CONF_CLK2OFFDS | USB_CONF_L1DS, &regs->usb_conf);
+	cdns3_set_register_bit(&regs->usb_conf, USB_CONF_CLK2OFFDS | USB_CONF_L1DS);

 	/* Set the Fast access bit */
 	writel(PUSB_PWR_FST_REG_ACCESS, &priv_dev->regs->usb_pwr);
@@ -2420,11 +2420,10 @@ static void cdns3_gadget_udc_set_speed(struct usb_gadget *gadget,

 	switch (speed) {
 	case USB_SPEED_FULL:
-		writel(USB_CONF_SFORCE_FS, &priv_dev->regs->usb_conf);
-		writel(USB_CONF_USB3DIS, &priv_dev->regs->usb_conf);
+	    cdns3_set_register_bit(&priv_dev->regs->usb_conf, USB_CONF_USB3DIS | USB_CONF_SFORCE_FS);
 		break;
 	case USB_SPEED_HIGH:
-		writel(USB_CONF_USB3DIS, &priv_dev->regs->usb_conf);
+	    cdns3_set_register_bit(&priv_dev->regs->usb_conf, USB_CONF_USB3DIS);
 		break;
 	case USB_SPEED_SUPER:
 		break;

So just to summarize:

Renan Santos Adriano said:
To flash our AM69 modules, we enter recovery mode and use DFU provided by the boot ROM to flash the U-Boot SPL on the R5 core of the SoC (tiboot3.bin built by U-Boot).

This part consistently works.

Then, the SPL runs on the R5 core and in turn starts a USB gadget providing DFU. This works most of the time, but not always. Sometimes, we observe that our gadget is never detected by the attached PC.

Debugging shows that in these cases the D+ line is never pulled up by the SoC, and therefore an attached PC will never see the gadget come up and will never try to enumerate this new USB device.

So, R5 SPL always comes up , but the stage after that fails.

Renan Santos Adriano said:
I have also written to the USB Config register (0x6020000) from `armv7/start.S` to test the behaviour of activating the D+ pullup as the first thing we do after reset. In this case, the pullup is always set correctly and the bug does not occur.

The bug does not occur in this case,right?

Renan Santos Adriano said:
My debugging took place on U-Boot v2024.04 but I have looked at and tested the changes in cdns3 upstream, there don't seem to be many.

The upstream driver does not fix the issue, right?

Ernest Van Hoecke said:
When I change the device tree to have usb0 use USB SuperSpeed, the bug occurs less often than when I change it to only use USB2, but it does not disappear. I

Using USB3.0 seems to improve the issue.

Regards

Gokul Praveen

0 Ernest Van Hoecke 6 days ago in reply to Gokul Praveen

Prodigy 110 points

Hi Gokul,

Thanks for your help.

How can I verify these SW2 settings? The port is in OTG/DR mode in the device tree to support the gadget.

Your patch did improve the statistics, I ran the below test:

```
GOOD BAD
GOKUL_ONLY_BIN : 3992 223
SS_NOPCIE0_BIN : 4210 4
SS_AND_PCIE0 : 4208 5
ALL_BIN : 4204 9
```

GOKUL_ONLY_BIN is the SPL with only your patch applied, no usage of USB SuperSpeed or any other changes.
SS_NOPCIE0_BIN is the SPL with USB SuperSpeed and pcie0 disabled, no changes to our SerDes configuration, and your patch not added.
SS_AND_PCIE0 is the SPL with USB SuperSpeed and the Serdes Configuration fixed, and PCIE0 still enabled, your patch not added.
ALL_BIN is the SPL with USB SS + SerDes config fixed and pcie0 enabled + your patch.

Now to answer your questions:

- The R5 SPL indeed always comes up, but occasionally fails to create the USB gadget. Specifically to set the pullup on D+.
- Correct, I never saw the bug when doing this from assembly right after reset. Maybe I should test again with even more boots.
- No, if you have a doubt I can test again with this tooling to compare side-by-side but it takes a good amount of time and I saw no promising patches.
- Yes, USB3.0 seems to drastically improve the issue.

We also have a doubt about this SerDes configuration. Can we expect different issues (aside from the one discussed here) with our current configuration? We were under the impression that the limit on the SerDes was 2 protocols, not 2 IPs. If that is wrong it is an immediate problem for us and we should find a solution. Any other tests I should run to verify that everything is okay? I have attached our full device trees (without any changes to the SerDes config for now) for your reference.

Kind regards,
Ernest

Fullscreen k3-am69-aquila-dev.dts.txt Download

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2024 Toradex
 *
 * Device tree for Toradex Aquila AM69 SoM on Aquila development carrier board
 *
 * https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69
 * https://www.toradex.com/products/carrier-board/aquila-development-board-kit
 */

/dts-v1/;

#include <dt-bindings/pwm/pwm.h>

#include "k3-j784s4.dtsi"
#include "k3-am69-aquila.dtsi"

/ {
	model = "Toradex Aquila AM69 on Aquila Development Board";
	compatible = "toradex,aquila-am69-dev",
		     "toradex,aquila-am69",
		     "ti,j784s4";

	aliases {
		eeprom1 = &carrier_eeprom;
	};

	reg_1v8_sw: regulator-1v8-sw {
		compatible = "regulator-fixed";
		regulator-max-microvolt = <1800000>;
		regulator-min-microvolt = <1800000>;
		regulator-name = "Carrier_1V8";
	};

	reg_3v3_dp: regulator-3v3-dp {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_21_dp>;
		enable-active-high;
		/* Aquila GPIO_21_DP (AQUILA B57) */
		gpio = <&main_gpio0 37 GPIO_ACTIVE_HIGH>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-name = "DP_3V3";
		startup-delay-us = <10000>;
	};

	dp0-connector {
		compatible = "dp-connector";
		dp-pwr-supply = <&reg_3v3_dp>;
		label = "Display Port";
		type = "full-size";

		port {
			dp0_connector_in: endpoint {
				remote-endpoint = <&dp0_out>;
			};
		};
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,bitclock-master = <&codec_dai>;
		simple-audio-card,format = "i2s";
		simple-audio-card,frame-master = <&codec_dai>;
		simple-audio-card,name = "aquila-wm8904";
		simple-audio-card,mclk-fs = <256>;
		simple-audio-card,routing =
			"Headphone Jack", "HPOUTL",
			"Headphone Jack", "HPOUTR",
			"IN2L", "Line In Jack",
			"IN2R", "Line In Jack",
			"Microphone Jack", "MICBIAS",
			"IN1L", "Microphone Jack",
			"IN1R", "Digital Mic";
		simple-audio-card,widgets =
			"Microphone", "Microphone Jack",
			"Microphone", "Digital Mic",
			"Headphone", "Headphone Jack",
			"Line", "Line In Jack";

		codec_dai: simple-audio-card,codec {
			sound-dai = <&wm8904_1a>;
		};

		simple-audio-card,cpu {
			sound-dai = <&mcasp4>;
		};
	};
};

/* Aquila CTRL_PWR_BTN_MICO# */
&aquila_key_power {
	status = "okay";
};

/* Aquila CTRL_WAKE1_MICO# */
&aquila_key_wake {
	status = "okay";
};

/* On-module ETH_1 MDIO */
&davinci_mdio {
	status = "okay";
};

&dp0_ports {
	port@4 {
		reg = <4>;
		dp0_out: endpoint {
			remote-endpoint = <&dp0_connector_in>;
		};
	};
};

&dss {
	status = "okay";
};

&main0_thermal {
	cooling-maps {
		map0 {
			cooling-device = <&fan 1 1>;
			trip = <&main0_alert0>;
		};

		map1 {
			cooling-device = <&fan 2 2>;
			trip = <&main0_alert1>;
		};
	};
};

&main1_thermal {
	cooling-maps {
		map0 {
			cooling-device = <&fan 1 1>;
			trip = <&main1_alert0>;
		};

		map1 {
			cooling-device = <&fan 2 2>;
			trip = <&main1_alert1>;
		};
	};
};

&main2_thermal {
	cooling-maps {
		map0 {
			cooling-device = <&fan 1 1>;
			trip = <&main2_alert0>;
		};

		map1 {
			cooling-device = <&fan 2 2>;
			trip = <&main2_alert1>;
		};
	};
};

&main3_thermal {
	cooling-maps {
		map0 {
			cooling-device = <&fan 1 1>;
			trip = <&main3_alert0>;
		};

		map1 {
			cooling-device = <&fan 2 2>;
			trip = <&main3_alert1>;
		};
	};
};

&main4_thermal {
	cooling-maps {
		map0 {
			cooling-device = <&fan 1 1>;
			trip = <&main4_alert0>;
		};

		map1 {
			cooling-device = <&fan 2 2>;
			trip = <&main4_alert1>;
		};
	};
};

/* Aquila ETH_2 */
&main_cpsw0 {
	status = "okay";
};

/* Aquila ETH_2 SGMII PHY */
&main_cpsw0_port8 {
	phy-handle = <&cpsw0_port8_phy4>;
	status = "okay";
};

/* Aquila ETH_2_XGMII_MDIO */
&main_cpsw0_mdio {
	status = "okay";

	cpsw0_port8_phy4: ethernet-phy@4 {
		reg = <4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_eth2_int>;
		interrupt-parent = <&main_gpio0>;
		interrupts = <44 IRQ_TYPE_EDGE_FALLING>;
	};
};

/* Aquila PWM_1 */
&main_ehrpwm0 {
	status = "okay";
};

/* Aquila PWM_4_DP */
&main_ehrpwm2 {
	status = "okay";
};

/* Aquila PWM_2 */
&main_ehrpwm1 {
	status = "okay";
};

/* Aquila PWM_3_DSI */
&main_ehrpwm5 {
	status = "okay";
};

&main_gpio0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_01>,  /* Aquila GPIO_01 */
		    <&pinctrl_gpio_02>,  /* Aquila GPIO_02 */
		    <&pinctrl_gpio_03>,  /* Aquila GPIO_03 */
		    <&pinctrl_usb1_en_gpio>;

	/* USB_1_EN Driven by Power Delivery IC - must be driven high */
	usb1en-hog {
		gpio-hog;
		gpios = <11 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "USB_1_EN";
	};
};

/* Aquila I2C_3_DSI1 */
&main_i2c0 {
	status = "okay";

	i2c-mux@70 {
		compatible = "nxp,pca9543";
		reg = <0x70>;
		#address-cells = <1>;
		#size-cells = <0>;

		/* I2C on DSI Connector Pin #4 and #6 */
		i2c_dsi_0: i2c@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		/* I2C on DSI Connector Pin #52 and #54 */
		i2c_dsi_1: i2c@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};
};

/* Aquila I2C_4_CSI1 */
&main_i2c1 {
	status = "okay";
};

/* Aquila I2C_5_CSI2 */
&main_i2c2 {
	status = "okay";
};

/* Aquila I2C_6 */
&main_i2c5 {
	status = "okay";
};

/* Aquila CAN_1 */
&main_mcan10 {
	status = "okay";
};

/* Aquila CAN_3 */
&main_mcan13 {
	status = "okay";
};

/* Aquila SD_1 */
&main_sdhci1 {
	status = "okay";
};

/* Aquila SPI_2 */
&main_spi0 {
	status = "okay";
};

/* Aquila SPI_1 */
&main_spi2 {
	status = "okay";
};

/* Aquila UART_1 */
&main_uart4 {
	status = "okay";
};

/* Aquila UART_3, used as the Linux console */
&main_uart8 {
	status = "okay";
};

/* Aquila I2S_1 */
&mcasp4 {
	status = "okay";
};

&mcu_cpsw {
	status = "okay";
};

/* On-module ETH_1 RGMII */
&mcu_cpsw_port1 {
	status = "okay";
};

/* Aquila I2C_1 */
&mcu_i2c0 {
	clock-frequency = <100000>;
	status = "okay";

	/* Fan controller */
	fan_controller: fan@18 {
		compatible = "ti,amc6821";
		reg = <0x18>;
		#pwm-cells = <2>;

		fan: fan {
			cooling-levels = <102 179 255>;
			#cooling-cells = <2>;
			pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>;
		};
	};

	/* Audio Codec */
	wm8904_1a: audio-codec@1a {
		compatible = "wlf,wm8904";
		reg = <0x1a>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_audio_extrefclk1>;
		#sound-dai-cells = <0>;
		clocks = <&audio_refclk1>;
		clock-names = "mclk";
		AVDD-supply = <&reg_1v8_sw>;
		CPVDD-supply = <&reg_1v8_sw>;
		DBVDD-supply = <&reg_1v8_sw>;
		DCVDD-supply = <&reg_1v8_sw>;
		MICVDD-supply = <&reg_1v8_sw>;

		wlf,drc-cfg-names = "default", "peaklimiter";
		/*
		 * Config registers per name, respectively:
		 * KNEE_IP = 0,   KNEE_OP = 0,     HI_COMP = 1,   LO_COMP = 1
		 * KNEE_IP = -24, KNEE_OP = -6,    HI_COMP = 1/4, LO_COMP = 1
		 */
		wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
				   /bits/ 16 <0x04af 0x324b 0x0010 0x0408>;

		/* GPIO1 = DMIC_CLK, don't touch others */
		wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;

		wlf,in1r-as-dmicdat2;
	};

	/* Current measurement into module VCC */
	hwmon@41 {
		compatible = "ti,ina226";
		reg = <0x41>;
		shunt-resistor = <5000>;
	};

	/* Temperature sensor */
	sensor@4f {
		compatible = "ti,tmp1075";
		reg = <0x4f>;
	};

	/* USB-C OTG (TCPC USB PD PHY) */
	ptn5110@52 {
		compatible = "nxp,ptn5110", "tcpci";
		reg = <0x52>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb1_int>;
		interrupt-parent = <&main_gpio0>;
		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;

		connector {
			compatible = "usb-c-connector";
			data-role = "dual";
			label = "USB-C OTG";
			power-role = "dual";
			try-power-role = "sink";
			self-powered;
			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
			sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
			op-sink-microwatt = <0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					usb_1_con_hs: endpoint {
						remote-endpoint = <&usb0_hs>;
					};
				};

				port@1 {
					reg = <1>;

					usb_1_con_ss: endpoint {
						remote-endpoint = <&usb0_ss_mux>;
					};
				};
			};
		};
	};

	/* EEPROM */
	carrier_eeprom: eeprom@57 {
		compatible = "st,24c02", "atmel,24c02";
		reg = <0x57>;
		pagesize = <16>;
	};
};

/* Aquila I2C_2 */
&mcu_i2c1 {
	status = "okay";
};

/* Aquila CAN_2 */
&mcu_mcan0 {
	status = "okay";
};

/* Aquila CAN_4 */
&mcu_mcan1 {
	status = "okay";
};

/* Aquila UART_4 */
&mcu_uart0 {
	status = "okay";
};

&mhdp {
	status = "okay";
};

/* Aquila QSPI_1 */
&ospi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mcu_ospi0_4bit>, <&pinctrl_mcu_ospi0_cs0>;
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-max-frequency = <66000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
		cdns,read-delay = <0>;
		cdns,tchsh-ns = <3>;
		cdns,tsd2d-ns = <10>;
		cdns,tshsl-ns = <30>;
		cdns,tslch-ns = <8>;
	};
};

/* Aquila PCIE_1 */
&pcie0_rc {
	status = "okay";
};

/* Aquila PCIE_2 */
&pcie1_rc {
	status = "okay";
};

&serdes2 {
	status = "okay";
};

&serdes4 {
	status = "okay";
};

&serdes_wiz2 {
	status = "okay";
};

&serdes_wiz4 {
	status = "okay";
};

/* Aquila ADC_[1-4] */
&tscadc0 {
	status = "okay";
};

&usbss0 {
	status = "okay";
};

&usb0ss_mux {
	status = "okay";

	port {
		usb0_ss_mux: endpoint {
			remote-endpoint = <&usb_1_con_ss>;
		};
	};
};

&usb0 {
	status = "okay";

	port {
		usb0_hs: endpoint {
			remote-endpoint = <&usb_1_con_hs>;
		};
	};
};

&wkup0_thermal {
	cooling-maps {
		map0 {
			cooling-device = <&fan 1 1>;
			trip = <&wkup0_alert0>;
		};

		map1 {
			cooling-device = <&fan 2 2>;
			trip = <&wkup0_alert1>;
		};
	};
};

&wkup1_thermal {
	cooling-maps {
		map0 {
			cooling-device = <&fan 1 1>;
			trip = <&wkup1_alert0>;
		};

		map1 {
			cooling-device = <&fan 2 2>;
			trip = <&wkup1_alert1>;
		};
	};
};

&wkup_gpio0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_04>,       /* Aquila GPIO_04 */
		    <&pinctrl_gpio_05>,       /* Aquila GPIO_05 */
		    <&pinctrl_gpio_06>,       /* Aquila GPIO_06 */
		    <&pinctrl_gpio_07>,       /* Aquila GPIO_07 */
		    <&pinctrl_gpio_08>;       /* Aquila GPIO_08 */
};

/* Aquila UART_2, through RS485 transceiver */
&wkup_uart0 {
	linux,rs485-enabled-at-boot-time;
	rs485-rx-during-tx;
	status = "okay";
};

Fullscreen k3-am69-aquila.dtsi.txt Download

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2024 Toradex
 *
 * Common dtsi for Toradex Aquila AM69 SoM
 *
 * https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/usb/pd.h>
#include "k3-j784s4.dtsi"

/ {
	chosen {
		stdout-path = "serial2:115200n8";
	};

	aliases {
		can0 = &main_mcan10;
		can1 = &mcu_mcan0;
		can2 = &main_mcan13;
		can3 = &mcu_mcan1;
		eeprom0 = &som_eeprom;
		ethernet0 = &mcu_cpsw_port1;
		ethernet1 = &main_cpsw0_port8;
		i2c0 = &wkup_i2c0;
		i2c1 = &mcu_i2c0;
		i2c2 = &mcu_i2c1;
		i2c3 = &main_i2c0;
		i2c4 = &main_i2c1;
		i2c5 = &main_i2c2;
		i2c6 = &main_i2c5;
		mmc0 = &main_sdhci0;
		mmc1 = &main_sdhci1;
		rtc0 = &rtc_i2c;
		serial0 = &main_uart4;
		serial1 = &wkup_uart0;
		serial2 = &main_uart8;
		serial3 = &mcu_uart0;
		usb0 = &usb0;
	};

	aquila_key_power: gpio-key-power {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pwr_btn_int>;
		status = "disabled";

		key-power {
			/* Aquila CTRL_PWR_BTN_MICO# (AQUILA B93) */
			gpios = <&wkup_gpio0 36 GPIO_ACTIVE_LOW>;
			label = "Power Button";
			linux,code = <KEY_POWER>;
		};
	};

	aquila_key_wake: gpio-key-wakeup {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ctrl_wake1_mico>;
		status = "disabled";

		key-wakeup {
			/* Aquila CTRL_WAKE1_MICO# (AQUILA D6) */
			gpios = <&wkup_gpio0 49 GPIO_ACTIVE_LOW>;
			label = "Wake Up";
			linux,code = <KEY_WAKEUP>;
			wakeup-source;
		};
	};

	/* Aquila CTRL_RESET_MICO# (AQUILA B92) */
	gpio-restart {
		compatible = "gpio-restart";
		/* COLD_RESET_REQ */
		gpios = <&som_gpio_expander 1 GPIO_ACTIVE_HIGH>;
		priority = <192>;
	};

	/* PWR_DOWN_REQ */
	gpio-poweroff {
		compatible = "gpio-poweroff";
		/* PWR_DOWN_REQ */
		gpios = <&som_gpio_expander 2 GPIO_ACTIVE_HIGH>;
		timeout-ms = <3000>;
	};

	memory@80000000 {
		device_type = "memory";
		/* 32G RAM */
		reg = <0x00 0x80000000 0x00 0x80000000>,
		      <0x08 0x80000000 0x07 0x80000000>;
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		secure_ddr: optee@9e800000 {
			reg = <0x00 0x9e800000 0x00 0x01800000>;
			no-map;
		};

		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0000000 0x00 0x100000>;
			no-map;
		};

		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0100000 0x00 0xf00000>;
			no-map;
		};

		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1000000 0x00 0x100000>;
			no-map;
		};

		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa4000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa4100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa5000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa5100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa6000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa6100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa7000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa7100000 0x00 0xf00000>;
			no-map;
		};

		c71_0_dma_memory_region: c71-dma-memory@a8000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa8000000 0x00 0x100000>;
			no-map;
		};

		c71_0_memory_region: c71-memory@a8100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa8100000 0x00 0xf00000>;
			no-map;
		};

		c71_1_dma_memory_region: c71-dma-memory@a9000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa9000000 0x00 0x100000>;
			no-map;
		};

		c71_1_memory_region: c71-memory@a9100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa9100000 0x00 0xf00000>;
			no-map;
		};

		c71_2_dma_memory_region: c71-dma-memory@aa000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xaa000000 0x00 0x100000>;
			no-map;
		};

		c71_2_memory_region: c71-memory@aa100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xaa100000 0x00 0xf00000>;
			no-map;
		};

		c71_3_dma_memory_region: c71-dma-memory@ab000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xab000000 0x00 0x100000>;
			no-map;
		};

		c71_3_memory_region: c71-memory@ab100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xab100000 0x00 0xf00000>;
			no-map;
		};
	};

	/* Module Power Supply (VCC) */
	reg_vin: regulator-vin {
		compatible = "regulator-fixed";
		regulator-name = "+V_IN";
	};

	/* Enabled by EN_3V3_VIO (PMIC_GPIO_9) */
	reg_1v1_usb_bridge: regulator-1v1-vio {
		compatible = "regulator-fixed";
		regulator-max-microvolt = <1100000>;
		regulator-min-microvolt = <1100000>;
		regulator-name = "+V1.1_VIO";
		vin-supply = <&reg_vin>;
	};

	reg_3v3_wifi: regulator-3v3-wifi {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_en_3v3_wifi>;
		enable-active-high;
		gpio = <&wkup_gpio0 57 GPIO_ACTIVE_HIGH>;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "+V3.3_WIFI";
		startup-delay-us = <20000>;
		vin-supply = <&reg_vin>;
	};

	reg_1v8_stby: regulator-1v8-stby {
		compatible = "regulator-fixed";
		regulator-max-microvolt = <1800000>;
		regulator-min-microvolt = <1800000>;
		regulator-name = "+V1.8_STBY";
		vin-supply = <&reg_vin>;
	};

	/* Aquila SD_1_PWR_EN */
	reg_sdhc1_vmmc: regulator-sdhci1 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_sd1_pwr_en>;
		enable-active-high;
		/* Aquila SD_1_PWR_EN (AQUILA A6) */
		gpio = <&main_gpio0 52 GPIO_ACTIVE_HIGH>;
		off-on-delay-us = <100000>;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "+3V3_SD";
		startup-delay-us = <20000>;
	};

	reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc {
		compatible = "regulator-gpio";
		/* SDIO_PWR_SEL_3.3V */
		gpios = <&som_gpio_expander 7 GPIO_ACTIVE_HIGH>;
		regulator-name = "+VDD_SD_DV";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		states = <1800000 0x0>,
			 <3300000 0x1>;
	};

	/* On-module USB_1_SS mux */
	usb0ss_mux: gpio-sbu-mux {
		compatible = "ti,tmuxhs4212", "gpio-sbu-mux";
		/* USB_MUX_SEL */
		select-gpios = <&som_gpio_expander 0 GPIO_ACTIVE_HIGH>;
		orientation-switch;
		status = "disabled";
	};
};

&main_pmx0 {
	/* Aquila DP_1_HPD */
	pinctrl_main_dp0_hpd: main-dp0-hpd-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */ /* AQUILA B59 */
		>;
	};

	/* Aquila PWM_1 */
	pinctrl_main_ehrpwm0_b: main-ehrpwm0b-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x064, PIN_OUTPUT, 9) /* (AF38) MCAN0_TX.EHRPWM0_B */ /* AQUILA C25 */
		>;
	};

	/* Aquila PWM_2 */
	pinctrl_main_ehrpwm1_a: main-ehrpwm1a-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x060, PIN_OUTPUT, 9) /* (AE36) MCASP2_AXR1.EHRPWM1_A */ /* AQUILA C26 */
		>;
	};

	/* Aquila PWM_3_DSI */
	pinctrl_main_ehrpwm5_a: main-ehrpwm5a-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x084, PIN_OUTPUT, 9) /* (AG38) MCASP0_AXR5.EHRPWM5_A */ /* AQUILA B46 */
		>;
	};

	/* Aquila PWM_4_DP */
	pinctrl_main_ehrpwm2_a: main-ehrpwm2a-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x040, PIN_INPUT, 9) /* (AF37) MCASP0_AXR0.EHRPWM2_A */ /* AQUILA B58 */
		>;
	};

	/* PMIC_INT# */
	pinctrl_pmic_int: main-gpio0-0-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTn.GPIO0_0 */
		>;
	};

	/* Aquila GPIO_09_CSI_1 */
	pinctrl_gpio_09_csi_1: main-gpio0-1-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ /* AQUILA B17 */
		>;
	};

	/* Aquila GPIO_10_CSI_1 */
	pinctrl_gpio_10_csi_1: main-gpio0-2-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ /* AQUILA B18 */
		>;
	};

	/* Aquila USB_1_OC# */
	pinctrl_usb1_oc: main-gpio0-10-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x028, PIN_INPUT, 7) /* (AE33) MCAN16_RX.GPIO0_10 */ /* AQUILA B75 */
		>;
	};

	/* Aquila USB_1_EN */
	pinctrl_usb1_en_gpio: main-gpio0-11-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x02c, PIN_INPUT, 7) /* (AL32) GPIO0_11 */ /* AQUILA B77 */
		>;
	};

	/* Aquila GPIO_17_DSI_1 */
	pinctrl_gpio_17_dsi_1: main-gpio0-12-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x030, PIN_INPUT, 7) /* (AK37) GPIO0_12 */ /* AQUILA B42 */
		>;
	};

	/* Aquila GPIO_19_DSI_1 */
	pinctrl_gpio_19_dsi_1: main-gpio0-13-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ /* AQUILA B44 */
		>;
	};

	/* Aquila GPIO_02 */
	pinctrl_gpio_02: main-gpio0-17-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x044, PIN_INPUT, 7) /* (AG37) MCASP0_AXR1.GPIO0_17 */ /* AQUILA D24 */
		>;
	};

	/* Aquila GPIO_20_DSI_1 */
	pinctrl_gpio_20_dsi_1: main-gpio0-18-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x048, PIN_INPUT, 7) /* (AK33) MCASP0_AXR2.GPIO0_18 */ /* AQUILA B45 */
		>;
	};

	/* Aquila GPIO_21_DP */
	pinctrl_gpio_21_dp: main-gpio0-21-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x054, PIN_INPUT, 7) /* (AD37) MCASP2_ACLKX.GPIO0_21 */ /* AQUILA B57 */
		>;
	};

	/* Aquila USB_1_INT# */
	pinctrl_usb1_int: main-gpio0-28-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x070, PIN_INPUT, 7) /* (AH38) MCAN1_RX.GPIO0_28 */ /* AQUILA B74 */
		>;
	};

	/* Aquila GPIO_03 */
	pinctrl_gpio_03: main-gpio0-29-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x074, PIN_INPUT, 7) /* (AC33) MCAN2_TX.GPIO0_29 */ /* AQUILA D25 */
		>;
	};

	/* Aquila GPIO_18_DSI_1 */
	pinctrl_gpio_18_dsi_1: main-gpio0-31-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x07c, PIN_INPUT, 7) /* (AJ38) MCASP0_AXR3.GPIO0_31 */ /* AQUILA B43 */
		>;
	};

	/* Aquila PCIE_1_RESET# */
	pinctrl_pcie0_reset: main-gpio0-32-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x080, PIN_INPUT, 7) /* (AK34) MCASP0_AXR4.GPIO0_32 */ /* AQUILA C38 */
		>;
	};

	/* Aquila PWM_3_DSI as GPIO */
	pinctrl_pwm3_dsi_gpio: main-gpio0-33-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x084, PIN_INPUT, 7) /* (AG38) MCASP0_AXR5.GPIO0_33 */ /* AQUILA B46 */
		>;
	};

	/* Aquila GPIO_01 */
	pinctrl_gpio_01: main-gpio0-34-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x088, PIN_INPUT, 7) /* (AF36) MCASP0_AXR6.GPIO0_34 */ /* AQUILA D23 */
		>;
	};

	/* Aquila PCIE_2_RESET# */
	pinctrl_pcie1_reset: main-gpio0-41-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0a4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ /* AQUILA C35 */
		>;
	};

	/* Aquila ETH_2_xGMII_INT# */
	pinctrl_eth2_int: main-gpio0-44-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 7) /* (AL33) MCASP1_AXR3.GPIO0_44 */ /* AQUILA B81 */
		>;
	};

	/* Aquila GPIO_11_CSI_1 */
	pinctrl_gpio_11_csi_1: main-gpio0-47-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0bc, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ /* AQUILA A11 */
		>;
	};

	/* Aquila GPIO_12_CSI_1 */
	pinctrl_gpio_12_csi_1: main-gpio0-48-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0c0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ /* AQUILA B19 */
		>;
	};

	/* Aquila SD_1_PWR_EN */
	pinctrl_sd1_pwr_en: main-gpio0-52-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0d0, PIN_INPUT, 7) /* (AP38) SPI0_CS1.GPIO0_52 */ /* AQUILA A6 */
		>;
	};

	/* Aquila SD_1_CD# as GPIO */
	pinctrl_sd1_cd_gpio: main-gpio0-58-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0e8, PIN_INPUT_PULLUP, 7) /* (AR38) TIMER_IO0.GPIO0_58 */ /* AQUILA A1 */
		>;
	};

	/* Aquila I2C_3_DSI1 */
	pinctrl_main_i2c0: main-i2c0-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0e0, PIN_INPUT, 0) /* (AN36) I2C0_SCL */ /* AQUILA B41 */
			J784S4_IOPAD(0x0e4, PIN_INPUT, 0) /* (AP37) I2C0_SDA */ /* AQUILA B40 */
			>;
	};

	/* Aquila I2C_4_CSI1 */
	pinctrl_main_i2c1: main-i2c1-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x020, PIN_INPUT_PULLUP, 12) /* (AJ35) MCAN15_RX.I2C1_SCL */ /* AQUILA A13 */
			J784S4_IOPAD(0x024, PIN_INPUT_PULLUP, 12) /* (AH34) MCAN16_TX.I2C1_SDA */ /* AQUILA A12 */
			>;
	};

	/* Aquila I2C_5_CSI2 */
	pinctrl_main_i2c2: main-i2c2-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x04c, PIN_INPUT_PULLUP, 13) /* (AC32) MCASP1_AXR1.I2C2_SCL */ /* AQUILA C6 */
			J784S4_IOPAD(0x050, PIN_INPUT_PULLUP, 13) /* (AC37) MCASP1_AXR2.I2C2_SDA */ /* AQUILA C5 */
			>;
	};

	/* Aquila I2C_6 */
	pinctrl_main_i2c5: main-i2c5-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x01c, PIN_INPUT_PULLUP, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ /* AQUILA C19 */
			J784S4_IOPAD(0x018, PIN_INPUT_PULLUP, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ /* AQUILA C18 */
			>;
	};

	/* Aquila I2S_1_MCLK */
	pinctrl_audio_extrefclk1: audio-extrefclk1-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */ /* AQUILA B24 */
		>;
	};

	/* Aquila CAN_1 */
	pinctrl_main_mcan10: main-mcan10-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0b8, PIN_INPUT, 0)  /* (AC34) MCASP1_ACLKX.MCAN10_RX */ /* AQUILA B49 */
			J784S4_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (AL34) MCASP1_AXR4.MCAN10_TX  */ /* AQUILA B48 */
		>;
	};

	/* Aquila CAN_3 */
	pinctrl_main_mcan13: main-mcan13-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x010, PIN_INPUT, 0)  /* (AH33) MCAN13_RX */ /* AQUILA B54 */
			J784S4_IOPAD(0x00c, PIN_OUTPUT, 0) /* (AF33) MCAN13_TX */ /* AQUILA B53 */
		>;
	};

	/* Aquila I2S_1 */
	pinctrl_main_mcasp4: main-mcasp4-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0c8, PIN_INPUT, 1)  /* (AJ32) EXT_REFCLK1.MCASP4_ACLKX      */ /* AQUILA B20 */
			J784S4_IOPAD(0x06c, PIN_INPUT, 1)  /* (AJ37) MCAN1_TX.MCASP4_AFSX          */ /* AQUILA B21 */
			J784S4_IOPAD(0x068, PIN_OUTPUT, 1) /* (AE38) MCAN0_RX.MCASP4_AXR1          */ /* AQUILA B22 */
			J784S4_IOPAD(0x0c4, PIN_INPUT, 1)  /* (AD36) ECAP0_IN_APWM_OUT.MCASP4_AXR2 */ /* AQUILA B23 */
		>;
	};

	/* Aquila ETH_2_XGMII_MDIO */
	pinctrl_main_mdio1: main-mdio1-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x058, PIN_OUTPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC  */ /* AQUILA B90 */
			J784S4_IOPAD(0x05c, PIN_INPUT, 4)  /* (AC36) MCASP2_AXR0.MDIO1_MDIO */ /* AQUILA B89 */
		>;
	};

	/* Aquila SD_1 */
	pinctrl_main_mmc1: main-mmc1-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK  */ /* AQUILA A5  */
			J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD  */ /* AQUILA A7  */
			J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */
			J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ /* AQUILA A3  */
			J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ /* AQUILA A2  */
			J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ /* AQUILA A10 */
			J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ /* AQUILA A8  */
		>;
	};

	/* Aquila SPI_2 */
	pinctrl_main_spi0: main-spi0-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AN38) SPI0_CLK */ /* AQUILA D14 */
			J784S4_IOPAD(0x0d8, PIN_INPUT, 0)  /* (AM35) SPI0_D0  */ /* AQUILA D15 */
			J784S4_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (AM36) SPI0_D1  */ /* AQUILA D17 */
		>;
	};

	/* Aquila SPI_2 CS */
	pinctrl_main_spi0_cs0: main-spi0-cs0-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (AM37) SPI0_CS0 */ /* AQUILA D16 */
		>;
	};

	/* Aquila SPI_1 */
	pinctrl_main_spi2: main-spi2-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0a0, PIN_OUTPUT, 10) /* (AD34) MCASP0_AXR12.SPI2_CLK */ /* AQUILA D12 */
			J784S4_IOPAD(0x0a8, PIN_INPUT, 10)  /* (AF34) MCASP0_AXR14.SPI2_D0  */ /* AQUILA D10 */
			J784S4_IOPAD(0x0ac, PIN_OUTPUT, 10) /* (AE34) MCASP0_AXR15.SPI2_D1  */ /* AQUILA D11 */
			>;
	};

	/* Aquila SPI_1 CS */
	pinctrl_main_spi2_cs0: main-spi2-cs0-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x09c, PIN_OUTPUT, 10) /* (AF35) MCASP0_AXR11.SPI2_CS1 */ /* AQUILA D9 */
		>;
	};

	/* Aquila UART_1 */
	pinctrl_main_uart4: main-uart4-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x094, PIN_INPUT, 11)  /* (AG35) MCASP0_AXR9.UART4_CTSn  */ /* AQUILA B36 */
			J784S4_IOPAD(0x098, PIN_OUTPUT, 11) /* (AH36) MCASP0_AXR10.UART4_RTSn */ /* AQUILA B38 */
			J784S4_IOPAD(0x08c, PIN_INPUT, 11)  /* (AE35) MCASP0_AXR7.UART4_RXD   */ /* AQUILA B35 */
			J784S4_IOPAD(0x090, PIN_OUTPUT, 11) /* (AC35) MCASP0_AXR8.UART4_TXD   */ /* AQUILA B37 */
		>;
	};

	/* Aquila UART_3, used as the Linux console */
	pinctrl_main_uart8: main-uart8-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x038, PIN_INPUT, 11)  /* (AK35) MCASP0_ACLKX.UART8_RXD */ /* AQUILA D19 */
			J784S4_IOPAD(0x03c, PIN_OUTPUT, 11) /* (AK38) MCASP0_AFSX.UART8_TXD  */ /* AQUILA D20 */
		>;
	};
};

&wkup_pmx0 {
	/* Aquila QSPI_1 (4-bit) */
	pinctrl_mcu_ospi0_4bit: mcu-ospi0-4bit-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK  */ /* AQUILA B65 */
			J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0)  /* (B33) MCU_OSPI0_D0   */ /* AQUILA B68 */
			J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0)  /* (B32) MCU_OSPI0_D1   */ /* AQUILA B67 */
			J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0)  /* (C33) MCU_OSPI0_D2   */ /* AQUILA B61 */
			J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0)  /* (C35) MCU_OSPI0_D3   */ /* AQUILA B60 */
			J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0)  /* (C34) MCU_OSPI0_DQS  */ /* AQUILA B63 */
		>;
	};

	/* Aquila QSPI_1 (8-bit) */
	pinctrl_mcu_ospi0_8bit: mcu-ospi0-8bit-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK  */ /* AQUILA B65 */
			J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0)  /* (B33) MCU_OSPI0_D0   */ /* AQUILA B68 */
			J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0)  /* (B32) MCU_OSPI0_D1   */ /* AQUILA B67 */
			J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0)  /* (C33) MCU_OSPI0_D2   */ /* AQUILA B61 */
			J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0)  /* (C35) MCU_OSPI0_D3   */ /* AQUILA B60 */
			J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0)  /* (D33) MCU_OSPI0_D4   */ /* AQUILA B70 */
			J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0)  /* (D34) MCU_OSPI0_D5   */ /* AQUILA B71 */
			J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0)  /* (E34) MCU_OSPI0_D6   */ /* AQUILA B72 */
			J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0)  /* (E33) MCU_OSPI0_D7   */ /* AQUILA B73 */
			J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0)  /* (C34) MCU_OSPI0_DQS  */ /* AQUILA B63 */
		>;
	};

	/* Aquila QSPI_1_CS1# */
	pinctrl_mcu_ospi0_cs0: mcu-ospi0-cs0-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ /* AQUILA B66 */
		>;
	};

	/* Aquila QSPI_1_CS2# */
	pinctrl_mcu_ospi0_cs1: mcu-ospi0-cs1-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (A33) MCU_OSPI0_CSn1 */ /* AQUILA B62 */
		>;
	};

	/* Aquila QSPI_1_SCK as GPIO */
	pinctrl_wkup_gpio_16: wkup-gpio0-16-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (E32) MCU_OSPI0_CLK.WKUP_GPIO0_16 */ /* AQUILA B65 */
		>;
	};

	/* Aquila GPIO_04 */
	pinctrl_gpio_04: wkup-gpio0-17-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 7) /* (D32) MCU_OSPI0_LBCLKO.WKUP_GPIO0_17 */ /* AQUILA C20 */
		>;
	};

	/* Aquila QSPI_1_DQS as GPIO */
	pinctrl_wkup_gpio_18: wkup-gpio0-18-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 7) /* (C34) MCU_OSPI0_DQS.WKUP_GPIO0_18 */ /* AQUILA B63 */
		>;
	};

	/* Aquila QSPI_1_IO0 as GPIO */
	pinctrl_wkup_gpio_19: wkup-gpio0-19-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 7) /* (B33) MCU_OSPI0_D0.WKUP_GPIO0_19 */ /* AQUILA B68 */
		>;
	};

	/* Aquila QSPI_1_IO1 as GPIO */
	pinctrl_wkup_gpio_20: wkup-gpio0-20-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 7) /* (B32) MCU_OSPI0_D1.WKUP_GPIO0_20 */ /* AQUILA B67 */
		>;
	};

	/* Aquila QSPI_1_IO2 as GPIO */
	pinctrl_wkup_gpio_21: wkup-gpio0-21-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 7) /* (C33) MCU_OSPI0_D2.WKUP_GPIO0_21 */ /* AQUILA B61 */
		>;
	};

	/* Aquila QSPI_1_IO3 as GPIO */
	pinctrl_wkup_gpio_22: wkup-gpio0-22-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 7) /* (C35) MCU_OSPI0_D3.WKUP_GPIO0_22 */ /* AQUILA B60 */
		>;
	};

	/* Aquila QSPI_1_IO4 as GPIO */
	pinctrl_wkup_gpio_23: wkup-gpio0-23-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 7) /* (D33) MCU_OSPI0_D4.WKUP_GPIO0_23 */ /* AQUILA B70 */
		>;
	};

	/* Aquila QSPI_1_IO5 as GPIO */
	pinctrl_wkup_gpio_24: wkup-gpio0-24-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 7) /* (D34) MCU_OSPI0_D5.WKUP_GPIO0_24 */ /* AQUILA B71 */
		>;
	};

	/* Aquila QSPI_1_IO6 as GPIO */
	pinctrl_wkup_gpio_25: wkup-gpio0-25-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 7) /* (E34) MCU_OSPI0_D6.WKUP_GPIO0_25 */ /* AQUILA B72 */
		>;
	};

	/* Aquila QSPI_1_IO7 as GPIO */
	pinctrl_wkup_gpio_26: wkup-gpio0-26-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) /* (E33) MCU_OSPI0_D7.WKUP_GPIO0_26 */ /* AQUILA B73 */
		>;
	};

	/* Aquila QSPI_1_CS#1 as GPIO */
	pinctrl_wkup_gpio_27: wkup-gpio0-27-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 7) /* (A32) MCU_OSPI0_CSn0.WKUP_GPIO0_27 */ /* AQUILA B66 */
		>;
	};

	/* Aquila QSPI_1_CS#2 as GPIO */
	pinctrl_wkup_gpio_28: wkup-gpio0-28-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 7) /* (A33) MCU_OSPI0_CSn1.WKUP_GPIO0_28 */ /* AQUILA B62 */
		>;
	};
};

&wkup_pmx1 {
	/* Aquila UART_4 (RXD) */
	pinctrl_mcu_uart0_rx: mcu-uart0-rx-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 4)  /* (D31) MCU_OSPI1_D1.MCU_UART0_RXD */ /* AQUILA D21 */
		>;
	};

	/* Aquila GPIO_05 */
	pinctrl_gpio_05: wkup-gpio0-29-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (B34) MCU_OSPI0_CSn2.WKUP_GPIO0_29 */ /* AQUILA C21 */
		>;
	};

	/* Aquila GPIO_06 */
	pinctrl_gpio_06: wkup-gpio0-30-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 7) /* (C32) MCU_OSPI0_CSn3.WKUP_GPIO0_30 */ /* AQUILA C22 */
		>;
	};

	/* Aquila GPIO_07 */
	pinctrl_gpio_07: wkup-gpio0-31-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 7) /* (F32) MCU_OSPI1_CLK.WKUP_GPIO0_31 */ /* AQUILA C23 */
		>;
	};

	/* Aquila GPIO_13_CSI_2 */
	pinctrl_gpio_13_csi_2: wkup-gpio0-32-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 7) /* (C31) MCU_OSPI1_LBCLKO.WKUP_GPIO0_32 */ /* AQUILA C1 */
		>;
	};

	/* Aquila GPIO_14_CSI_2 */
	pinctrl_gpio_14_csi_2: wkup-gpio0-33-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 7) /* (F31) MCU_OSPI1_DQS.WKUP_GPIO0_33 */ /* AQUILA C2 */
		>;
	};

	/* RTC_IRQ# */
	pinctrl_rtc_irq: wkup-gpio0-34-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 7) /* (E35) MCU_OSPI1_D0.WKUP_GPIO0_34 */
		>;
	};

	/* Aquila CTRL_PWR_BTN_MICO# (PWR_BTN_INT#) */
	pinctrl_pwr_btn_int: wkup-gpio0-36-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x01c, PIN_INPUT_PULLUP, 7) /* (G31) MCU_OSPI1_D2.WKUP_GPIO0_36 */ /* AQUILA B92 */
		>;
	};

	/* Aquila GPIO_15_CSI_2 */
	pinctrl_gpio_15_csi_2: wkup-gpio0-37-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 7) /* (F33) MCU_OSPI1_D3.WKUP_GPIO0_37 */ /* AQUILA C3 */
		>;
	};

	/* Aquila GPIO_08 */
	pinctrl_gpio_08: wkup-gpio0-38-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 7) /* (G32) MCU_OSPI1_CSn0.WKUP_GPIO0_38 */ /* AQUILA C24 */
		>;
	};

	/* Aquila GPIO_16_CSI_2 */
	pinctrl_gpio_16_csi_2: wkup-gpio0-39-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ /* AQUILA C4 */
		>;
	};
};

&wkup_pmx2 {
	/* Aquila ADC_[1-4] */
	pinctrl_mcu_adc0: mcu-adc0-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (P36) MCU_ADC0_AIN0 */ /* AQUILA D1 */
			J784S4_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (V36) MCU_ADC0_AIN1 */ /* AQUILA D2 */
			J784S4_WKUP_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (T34) MCU_ADC0_AIN2 */ /* AQUILA D3 */
			J784S4_WKUP_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (T36) MCU_ADC0_AIN3 */ /* AQUILA D4 */
		>;
	};

	/* Aquila CTRL_MCLK_MOCI */
	pinctrl_mcu_clkout0: mcu-clkout0-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x084, PIN_OUTPUT, 6) /* (M38) WKUP_GPIO0_11.MCU_CLKOUT0 */ /* AQUILA A14 */
		>;
	};

	/* Aquila I2C_1 */
	pinctrl_mcu_i2c0: mcu-i2c0-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (M35) MCU_I2C0_SCL */ /* AQUILA D8 */
			J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (G34) MCU_I2C0_SDA */ /* AQUILA D7 */
		>;
	};

	/* Aquila I2C_2 */
	pinctrl_mcu_i2c1: mcu-i2c1-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0) /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */ /* AQUILA C17 */
			J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0) /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */ /* AQUILA C16 */
		>;
	};

	/* Aquila CAN_2 */
	pinctrl_mcu_mcan0: mcu-mcan0-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0)  /* (F38) MCU_MCAN0_RX  */ /* AQUILA B51 */
			J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX  */ /* AQUILA B50 */
		>;
	};

	/* Aquila CAN_4 */
	pinctrl_mcu_mcan1: mcu-mcan1-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0)  /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ /* AQUILA B56 */
			J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ /* AQUILA B55 */
		>;
	};

	/* On-module ETH_1 MDIO */
	pinctrl_mcu_mdio: mcu-mdio-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC  */
			J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0)  /* (B35) MCU_MDIO0_MDIO */
		>;
	};

	/* On-module ETH_1 RGMII */
	pinctrl_mcu_rgmii1: mcu-rgmii1-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0)  /* (A35) MCU_RGMII1_RD0    */
			J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0)  /* (B36) MCU_RGMII1_RD1    */
			J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0)  /* (C36) MCU_RGMII1_RD2    */
			J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0)  /* (D36) MCU_RGMII1_RD3    */
			J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0)  /* (B37) MCU_RGMII1_RXC    */
			J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0)  /* (C37) MCU_RGMII1_RX_CTL */
			J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0    */
			J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1    */
			J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2    */
			J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3    */
			J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC    */
			J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
		>;
	};

	/* On-module SPI (TPM_SPI) */
	pinctrl_mcu_spi0: mcu-spi0-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (G38) MCU_SPI0_CLK */
			J784S4_WKUP_IOPAD(0x044, PIN_OUTPUT, 0) /* (F37) MCU_SPI0_CS0 */
			J784S4_WKUP_IOPAD(0x03c, PIN_INPUT, 0)  /* (H36) MCU_SPI0_D0  */
			J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (J38) MCU_SPI0_D1  */
		>;
	};

	/* Aquila UART_4 (TX) */
	pinctrl_mcu_uart0_tx: mcu-uart0-tx-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 2) /* (L33) WKUP_GPIO0_10.MCU_UART0_TXD */ /* AQUILA D22 */
		>;
	};

	/* On-module Wi-Fi Power Enable */
	pinctrl_en_3v3_wifi: wkup-gpio0-57-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */
		>;
	};

	/* On-module TPM IRQ# */
	pinctrl_tpm_irq: wkup-gpio0-81-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 7) /* (V34) MCU_ADC1_AIN2.WKUP_GPIO0_81 */
		>;
	};

	/* On-module I2C - WKUP_I2C0 */
	pinctrl_wkup_i2c0: wkup-i2c0-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */
			J784S4_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
		>;
	};

	/* Aquila UART_2 */
	pinctrl_wkup_uart0: wkup-uart0-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 0)  /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ /* AQUILA B32 */
			J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ /* AQUILA B34 */
			J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0)  /* (K35) WKUP_UART0_RXD               */ /* AQUILA B31 */
			J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD               */ /* AQUILA B33 */
		>;
	};
};

&wkup_pmx3 {
	/* Aquila CTRL_WAKE1_MICO# */
	pinctrl_ctrl_wake1_mico: wkup-gpio0-49-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x000, PIN_INPUT_PULLUP, 7) /* (M33) WKUP_GPIO0_49 */ /* AQUILA D6 */
		>;
	};
};

/* Aquila I2S_1_MCLK */
&audio_refclk1 {
	assigned-clock-rates = <24576000>;
};

&c71_0 {
	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
	memory-region = <&c71_0_dma_memory_region>,
			<&c71_0_memory_region>;
	status = "okay";
};

&c71_1 {
	mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
	memory-region = <&c71_1_dma_memory_region>,
			<&c71_1_memory_region>;
	status = "okay";
};

&c71_2 {
	mboxes = <&mailbox0_cluster5 &mbox_c71_2>;
	memory-region = <&c71_2_dma_memory_region>,
			<&c71_2_memory_region>;
	status = "okay";
};

&c71_3 {
	mboxes = <&mailbox0_cluster5 &mbox_c71_3>;
	memory-region = <&c71_3_dma_memory_region>,
			<&c71_3_memory_region>;
	status = "okay";
};

/* On-module ETH_1 MDIO */
&davinci_mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mcu_mdio>;
	status = "disabled";

	mcu_phy0: ethernet-phy@0 {
		reg = <0>;
		interrupt-parent = <&wkup_gpio0>;
		interrupts = <79 IRQ_TYPE_EDGE_FALLING>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	};
};

&dss {
	/* TODO: Validate the functionality without this. If found redundant, remove */
	assigned-clocks = <&k3_clks 218 2>,
			  <&k3_clks 218 5>,
			  <&k3_clks 218 14>,
			  <&k3_clks 218 18>;
	assigned-clock-parents = <&k3_clks 218 3>,
				 <&k3_clks 218 7>,
				 <&k3_clks 218 16>,
				 <&k3_clks 218 22>;
	status = "disabled";
};

&dss_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
		reg = <0>;
		dpi0_out: endpoint {
			remote-endpoint = <&dp0_in>;
		};
	};
};

&dp0_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
		reg = <0>;
		dp0_in: endpoint {
			remote-endpoint = <&dpi0_out>;
		};
	};
};

&main0_crit {
	temperature = <105000>;
};

&main0_thermal {
	trips {
		main0_alert0: trip-point0 {
			temperature = <70000>;
			hysteresis = <2000>;
			type = "active";
		};

		main0_alert1: trip-point1 {
			temperature = <85000>;
			hysteresis = <2000>;
			type = "active";
		};
	};
};

&main1_crit {
	temperature = <105000>;
};

&main1_thermal {
	trips {
		main1_alert0: trip-point0 {
			temperature = <70000>;
			hysteresis = <2000>;
			type = "active";
		};

		main1_alert1: trip-point1 {
			temperature = <85000>;
			hysteresis = <2000>;
			type = "active";
		};
	};
};

&main2_crit {
	temperature = <105000>;
};

&main2_thermal {
	trips {
		main2_alert0: trip-point0 {
			temperature = <70000>;
			hysteresis = <2000>;
			type = "active";
		};

		main2_alert1: trip-point1 {
			temperature = <85000>;
			hysteresis = <2000>;
			type = "active";
		};
	};
};

&main3_crit {
	temperature = <105000>;
};

&main3_thermal {
	trips {
		main3_alert0: trip-point0 {
			temperature = <70000>;
			hysteresis = <2000>;
			type = "active";
		};

		main3_alert1: trip-point1 {
			temperature = <85000>;
			hysteresis = <2000>;
			type = "active";
		};
	};
};

&main4_crit {
	temperature = <105000>;
};

&main4_thermal {
	trips {
		main4_alert0: trip-point0 {
			temperature = <70000>;
			hysteresis = <2000>;
			type = "active";
		};

		main4_alert1: trip-point1 {
			temperature = <85000>;
			hysteresis = <2000>;
			type = "active";
		};
	};
};

/* Aquila ETH_2 SGMII PHY */
&main_cpsw0_port8 {
	phy-mode = "sgmii";
	phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_sgmii_link>;
	phy-names = "mac", "serdes";
	status = "disabled";
};

/* Aquila ETH_2_XGMII_MDIO */
&main_cpsw0_mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_mdio1>;
};

/* Aquila PWM_1 */
&main_ehrpwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_ehrpwm0_b>;
	status = "disabled";
};

/* Aquila PWM_2 */
&main_ehrpwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_ehrpwm1_a>;
	status = "disabled";
};

/* Aquila PWM_4_DP */
&main_ehrpwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_ehrpwm2_a>;
	status = "disabled";
};

/* Aquila PWM_3_DSI */
&main_ehrpwm5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_ehrpwm5_a>;
	status = "disabled";
};

&main_gpio0 {
	gpio-line-names =
		"", /* 0 */
		"AQUILA_B17",
		"AQUILA_B18",
		"AQUILA_B53",
		"AQUILA_B54",
		"AQUILA_B59",
		"AQUILA_C18",
		"AQUILA_C19",
		"AQUILA_A13",
		"AQUILA_A12",
		"AQUILA_B75", /* 10 */
		"AQUILA_B77",
		"AQUILA_B42",
		"AQUILA_B44",
		"AQUILA_D19",
		"AQUILA_D20",
		"AQUILA_B58",
		"AQUILA_D24",
		"AQUILA_B45",
		"AQUILA_C06",
		"AQUILA_C05", /* 20 */
		"AQUILA_B57",
		"AQUILA_B90",
		"AQUILA_B89",
		"AQUILA_C26",
		"AQUILA_C25",
		"AQUILA_B22",
		"AQUILA_B21",
		"AQUILA_B74",
		"AQUILA_D25",
		"AQUILA_B24", /* 30 */
		"AQUILA_B43",
		"AQUILA_C38",
		"AQUILA_B46",
		"AQUILA_D23",
		"AQUILA_B35",
		"AQUILA_B37",
		"AQUILA_B36",
		"AQUILA_B38",
		"AQUILA_D09",
		"AQUILA_D12", /* 40 */
		"AQUILA_C35",
		"AQUILA_D10",
		"AQUILA_D11",
		"AQUILA_B81",
		"AQUILA_B48",
		"AQUILA_B49",
		"AQUILA_A11",
		"AQUILA_B19",
		"AQUILA_B23",
		"AQUILA_B20", /* 50 */
		"AQUILA_D16",
		"AQUILA_A06",
		"AQUILA_D14",
		"AQUILA_D15",
		"AQUILA_D17",
		"AQUILA_B41",
		"AQUILA_B40",
		"AQUILA_A01",
		"",
		"AQUILA_A08", /* 60 */
		"AQUILA_A10",
		"AQUILA_A02",
		"AQUILA_A03",
		"AQUILA_A05",
		"AQUILA_A07";

	status = "okay";
};

/* Aquila I2C_3_DSI1 */
&main_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_i2c0>;
	clock-frequency = <100000>;
	status = "disabled";
};

/* Aquila I2C_4_CSI1 */
&main_i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_i2c1>;
	clock-frequency = <400000>;
	status = "disabled";
};

/* Aquila I2C_5_CSI2 */
&main_i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_i2c2>;
	clock-frequency = <400000>;
	status = "disabled";
};

/* Aquila I2C_6 */
&main_i2c5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_i2c5>;
	clock-frequency = <400000>;
	status = "disabled";
};

&mailbox0_cluster0 {
	interrupts = <436>;
	status = "okay";

	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster1 {
	interrupts = <432>;
	status = "okay";

	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster2 {
	interrupts = <428>;
	status = "okay";

	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster3 {
	interrupts = <424>;
	status = "okay";

	mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster4 {
	interrupts = <420>;
	status = "okay";

	mbox_c71_0: mbox-c71-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_c71_1: mbox-c71-1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster5 {
	interrupts = <416>;
	status = "okay";

	mbox_c71_2: mbox-c71-2 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_c71_3: mbox-c71-3 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

/* Aquila CAN_1 */
&main_mcan10 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_mcan10>;
	status = "disabled";
};

/* Aquila CAN_3 */
&main_mcan13 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_mcan13>;
	status = "disabled";
};

&main_r5fss0_core1 {
	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
	memory-region = <&main_r5fss0_core1_dma_memory_region>,
			<&main_r5fss0_core1_memory_region>;
	status = "okay";
};

&main_r5fss1_core0 {
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
	memory-region = <&main_r5fss1_core0_dma_memory_region>,
			<&main_r5fss1_core0_memory_region>;
	status = "okay";
};

&main_r5fss1_core1 {
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
	memory-region = <&main_r5fss1_core1_dma_memory_region>,
			<&main_r5fss1_core1_memory_region>;
	status = "okay";
};

&main_r5fss2_core0 {
	mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>;
	memory-region = <&main_r5fss2_core0_dma_memory_region>,
			<&main_r5fss2_core0_memory_region>;
	status = "okay";
};

&main_r5fss2_core1 {
	mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>;
	memory-region = <&main_r5fss2_core1_dma_memory_region>,
			<&main_r5fss2_core1_memory_region>;
	status = "okay";
};

/* On-module eMMC */
&main_sdhci0 {
	disable-wp;
	non-removable;
	ti,driver-strength-ohm = <50>;
	status = "okay";
};

/* Aquila SD_1 */
&main_sdhci1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_mmc1>, <&pinctrl_sd1_cd_gpio>;
	cd-gpios = <&main_gpio0 58 GPIO_ACTIVE_LOW>;
	disable-wp;
	vmmc-supply = <&reg_sdhc1_vmmc>;
	vqmmc-supply = <&reg_sdhc1_vqmmc>;
	ti,driver-strength-ohm = <50>;
	ti,fails-without-test-cd;
	status = "disabled";
};

/* Aquila SPI_2 */
&main_spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_spi0>, <&pinctrl_main_spi0_cs0>;
	status = "disabled";
};

/* Aquila SPI_1 */
&main_spi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_spi2>, <&pinctrl_main_spi2_cs0>;
	status = "disabled";
};

/* Aquila UART_1 */
&main_uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_uart4>;
	status = "disabled";
};

/* Aquila UART_3, used as the Linux console */
&main_uart8 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_uart8>;
	status = "disabled";
};

/* Aquila I2S_1 */
&mcasp4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_mcasp4>;
	op-mode = <0>;  /* MCASP_I2S_MODE */
	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		0 1 2 0
		0 0 0 0
		0 0 0 0
		0 0 0 0
	>;
	tdm-slots = <2>;
	#sound-dai-cells = <0>;
	status = "disabled";
};

&mcu_cpsw {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mcu_rgmii1>;
	status = "disabled";
};

/* On-module ETH_1 RGMII */
&mcu_cpsw_port1 {
	phy-handle = <&mcu_phy0>;
	phy-mode = "rgmii-rxid";
	status = "disabled";
};

/* Aquila I2C_1 */
&mcu_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mcu_i2c0>;
	clock-frequency = <400000>;
	status = "disabled";
};

/* Aquila I2C_2 */
&mcu_i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mcu_i2c1>;
	clock-frequency = <400000>;
	status = "disabled";
};

/* Aquila CAN_2 */
&mcu_mcan0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mcu_mcan0>;
	status = "disabled";
};

/* Aquila CAN_4 */
&mcu_mcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mcu_mcan1>;
	status = "disabled";
};

&mcu_r5fss0_core0 {
	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
			<&mcu_r5fss0_core0_memory_region>;
	status = "okay";
};

&mcu_r5fss0_core1 {
	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
			<&mcu_r5fss0_core1_memory_region>;
	status = "okay";
};

/* On-module SPI (TPM_SPI) */
&mcu_spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mcu_spi0>;
	status = "okay";

	tpm@0 {
		compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
		reg = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_tpm_irq>;
		interrupt-parent = <&wkup_gpio0>;
		interrupts = <81 IRQ_TYPE_EDGE_FALLING>;
		spi-max-frequency = <33000000>;
	};
};

/* Aquila UART_4 */
&mcu_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mcu_uart0_rx>, <&pinctrl_mcu_uart0_tx>;
	status = "disabled";
};

&mhdp {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_dp0_hpd>;
	phy-names = "dpphy";
	phys = <&serdes4_dp0_link>;
	status = "disabled";
};

/* Aquila QSPI_1 */
&ospi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mcu_ospi0_8bit>, <&pinctrl_mcu_ospi0_cs0>;
	status = "disabled";
};

/* Aquila PCIE_1 */
&pcie0_rc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0_reset>;
	clocks = <&k3_clks 332 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
	clock-names = "fck", "pcie_refclk";
	num-lanes = <2>;
	phy-names = "pcie-phy";
	phys = <&serdes1_pcie0_2l_link>;
	reset-gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>;
	ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x3>;
	status = "disabled";
};

/* Aquila PCIE_2 */
&pcie1_rc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie1_reset>;
	clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
	clock-names = "fck", "pcie_refclk";
	num-lanes = <2>;
	phy-names = "pcie-phy";
	phys = <&serdes0_pcie1_2l_link>;
	reset-gpios = <&main_gpio0 41 GPIO_ACTIVE_HIGH>;
	ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>;
	status = "disabled";
};

/* On-module PCIe USB Bridge */
&pcie2_rc {
	clocks = <&k3_clks 334 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
	clock-names = "fck", "pcie_refclk";
	num-lanes = <1>;
	phy-names = "pcie-phy";
	phys = <&serdes1_pcie2_1l_link>;
	reset-gpios = <&som_gpio_expander 3 GPIO_ACTIVE_HIGH>;
	ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x3>;
	status = "okay";

	pci@0,0 {
		device_type = "pci";
		reg = <0x0 0x0 0x0 0x0 0x0>;

		#address-cells = <3>;
		#size-cells = <2>;
		ranges;

		usb@0 {
			compatible = "pci104c,8241";
			reg = <0x0 0x0 0x0 0x0 0x0>;
			ti,pwron-active-high;
		};
	};
};

/* PCIE for On-module Wi-Fi */
&pcie3_rc {
	clocks = <&k3_clks 335 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
	clock-names = "fck", "pcie_refclk";
	num-lanes = <1>;
	phy-names = "pcie-phy";
	phys = <&serdes0_pcie3_1l_link>;
	reset-gpios = <&som_gpio_expander 4 GPIO_ACTIVE_HIGH>;
	vpcie3v3-supply = <&reg_3v3_wifi>;
	ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>;
	status = "okay";
};

&serdes0 {
	status = "okay";

	/* Aquila PCIE_2 */
	serdes0_pcie1_2l_link: phy@0 {
		reg = <0>;
		#phy-cells = <0>;
		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
		cdns,num-lanes = <2>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
	};

	/* On-module PCIe Wi-Fi */
	serdes0_pcie3_1l_link: phy@2 {
		reg = <2>;
		#phy-cells = <0>;
		resets = <&serdes_wiz0 3>;
		cdns,num-lanes = <1>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
	};

	/* Aquila USB0 SS */
	serdes0_usb0_ss_link: phy@3 {
		reg = <3>;
		#phy-cells = <0>;
		resets = <&serdes_wiz0 4>;
		cdns,num-lanes = <1>;
		cdns,phy-type = <PHY_TYPE_USB3>;
	};
};

&serdes1 {
	status = "okay";

	/* Aquila PCIE_1 */
	serdes1_pcie0_2l_link: phy@0 {
		reg = <0>;
		#phy-cells = <0>;
		resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
		cdns,num-lanes = <2>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
	};

	/* On-module PCIe USB Bridge */
	serdes1_pcie2_1l_link: phy@2 {
		reg = <2>;
		#phy-cells = <0>;
		resets = <&serdes_wiz1 3>;
		cdns,num-lanes = <1>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
	};
};

&serdes2 {
	status = "disabled";

	/* Aquila ETH_2 xGMII */
	serdes2_sgmii_link: phy@3 {
		reg = <3>;
		#phy-cells = <0>;
		resets = <&serdes_wiz2 4>;
		cdns,num-lanes = <1>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
	};
};

&serdes4 {
	status = "disabled";

	/* Aquila DP_1 */
	serdes4_dp0_link: phy@0 {
		reg = <0>;
		#phy-cells = <0>;
		resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
			 <&serdes_wiz4 3>, <&serdes_wiz4 4>;
		cdns,max-bit-rate = <5400>;
		cdns,num-lanes = <4>;
		cdns,phy-type = <PHY_TYPE_DP>;
	};
};

&serdes_refclk {
	clock-frequency = <100000000>;
	status = "okay";
};

&serdes_ln_ctrl {
	idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,     /* Aquila PCIE_2 L0          */
		      <J784S4_SERDES0_LANE1_PCIE1_LANE1>,     /* Aquila PCIE_2 L1          */
		      <J784S4_SERDES0_LANE2_PCIE3_LANE0>,     /* On-module PCIe Wi-Fi      */
		      <J784S4_SERDES0_LANE3_USB>,             /* Aquila USB0 SS            */
		      <J784S4_SERDES1_LANE0_PCIE0_LANE0>,     /* Aquila PCIE_1 L0          */
		      <J784S4_SERDES1_LANE1_PCIE0_LANE1>,     /* Aquila PCIE_1 L1          */
		      <J784S4_SERDES1_LANE2_PCIE2_LANE0>,     /* On-module PCIe USB Bridge */
		      <J784S4_SERDES1_LANE3_QSGMII_LANE2>,    /* Aquila SGMII MSP_9        */
		      <J784S4_SERDES2_LANE0_QSGMII_LANE5>,    /* Aquila SGMII MSP_6        */
		      <J784S4_SERDES2_LANE1_QSGMII_LANE6>,    /* Aquila SGMII MSP_7        */
		      <J784S4_SERDES2_LANE2_QSGMII_LANE7>,    /* Aquila SGMII MSP_8        */
		      <J784S4_SERDES2_LANE3_QSGMII_LANE8>,    /* Aquila ETH_2 xGMII        */
		      <J784S4_SERDES4_LANE0_EDP_LANE0>,       /* Aquila DP L0              */
		      <J784S4_SERDES4_LANE1_EDP_LANE1>,       /* Aquila DP L1              */
		      <J784S4_SERDES4_LANE2_EDP_LANE2>,       /* Aquila DP L2              */
		      <J784S4_SERDES4_LANE3_EDP_LANE3>;       /* Aquila DP L3              */
};

&serdes_wiz0 {
	status = "okay";
};

&serdes_wiz1 {
	status = "okay";
};

&serdes_wiz2 {
	status = "disabled";
};

&serdes_wiz4 {
	status = "disabled";
};

/* Aquila ADC_[1-4] */
&tscadc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mcu_adc0>;
	status = "disabled";

	adc {
		ti,adc-channels = <0 1 2 3>;
	};
};

&usb0 {
	phys = <&serdes0_usb0_ss_link>;
	phy-names = "cdns3,usb3-phy";
	dr_mode = "otg";
	maximum-speed = "super-speed";
	usb-role-switch;
	status = "disabled";
};

&usb_serdes_mux {
	idle-states = <0>; /* USB0 to SERDES lane 3 */
};

&usbss0 {
	ti,vbus-divider;
	status = "disabled";
};

&wkup_gpio0 {
	gpio-line-names =
		"", /* 0 */
		"",
		"",
		"AQUILA_C53",
		"AQUILA_B55",
		"AQUILA_B56",
		"AQUILA_B32",
		"AQUILA_B34",
		"AQUILA_C17",
		"AQUILA_C16",
		"AQUILA_D22", /* 10 */
		"",
		"",
		"",
		"",
		"",
		"AQUILA_B65",
		"AQUILA_C20",
		"AQUILA_B63",
		"AQUILA_B68",
		"AQUILA_B67", /* 20 */
		"AQUILA_B61",
		"AQUILA_B60",
		"AQUILA_B70",
		"AQUILA_B71",
		"AQUILA_B72",
		"AQUILC_B73",
		"AQUILA_B66",
		"AQUILA_B62",
		"AQUILA_C21",
		"AQUILA_C22", /* 30 */
		"AQUILA_C23",
		"AQUILA_C01",
		"AQUILA_C02",
		"",
		"AQUILA_D21",
		"",
		"AQUILA_C03",
		"AQUILA_C24",
		"AQUILA_C04",
		"AQUILA_B84", /* 40 */
		"",
		"AQUILA_B86",
		"AQUILA_B87",
		"",
		"",
		"AQUILA_B83",
		"",
		"",
		"",
		"", /* 50 */
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"AQUILA_B31",
		"AQUILA_B33",
		"AQUILA_B50", /* 60 */
		"AQUILA_B51",
		"",
		"",
		"",
		"AQUILA_D08",
		"",
		"",
		"",
		"",
		"", /* 70 */
		"AQUILA_D01",
		"AQUILA_D02",
		"AQUILA_D03",
		"AQUILA_D04",
		"AQUILA_D54",
		"AQUILA_D55",
		"AQUILA_C55",
		"AQUILA_C56",
		"",
		"AQUILA_C36", /* 80 */
		"",
		"",
		"",
		"",
		"",
		"",
		"AQUILA_D07",
		"";

	status = "okay";
};

/* On-module I2C - WKUP_I2C0 */
&wkup_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wkup_i2c0>;
	clock-frequency = <400000>;
	status = "okay";

	som_gpio_expander: gpio@21 {
		compatible = "ti,tca6408";
		reg = <0x21>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-line-names =
			"USB_MUX_SEL",
			"COLD_RESET_REQ",
			"PWR_DOWN_REQ",
			"PCIE_3_RESET#",
			"PCIE_4_RESET#",
			"WIFI_DISABLE",
			"BT_DISABLE",
			"SDIO_PWR_SEL_3.3V";
	};

	rtc_i2c: rtc@32 {
		compatible = "epson,rx8130";
		reg = <0x32>;
	};

	pmic_tps6594: pmic@48 {
		compatible = "ti,tps6594-q1";
		reg = <0x48>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic_int>;
		/* TODO : Explore option to use EXTINTN internal IRQ# */
		interrupt-parent = <&main_gpio0>;
		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;

		#gpio-cells = <2>;
		gpio-controller;

		buck12-supply = <&reg_vin>;
		buck3-supply = <&reg_vin>;
		buck4-supply = <&reg_vin>;
		buck5-supply = <&reg_vin>;
		ldo1-supply = <&reg_vin>;
		ldo2-supply = <&reg_vin>;
		ldo3-supply = <&reg_vin>;
		ldo4-supply = <&reg_vin>;
		system-power-controller;
		ti,primary-pmic;

		regulators {
			reg_vdd_ddr: buck12 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1100000>;
				regulator-min-microvolt = <1100000>;
				regulator-name = "+V1.1_VDD_DDR (PMIC BUCK12)";
			};

			reg_vdd_ram: buck3 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <850000>;
				regulator-min-microvolt = <850000>;
				regulator-name = "+V0.85_VDD_RAM (PMIC BUCK3)";
			};

			reg_vdd_io: buck4 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1800000>;
				regulator-min-microvolt = <1800000>;
				regulator-name = "+V1.8_VDD_IO (PMIC BUCK4)";
			};

			reg_3v3_vio: buck5 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <3300000>;
				regulator-min-microvolt = <3300000>;
				regulator-name = "+V3.3_VIO (PMIC BUCK5)";
			};

			reg_vda_phy: ldo1 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1800000>;
				regulator-min-microvolt = <1800000>;
				regulator-name = "+V1.8_VDA_PHY (PMIC LDO1)";
			};

			reg_2v5_eth: ldo2 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <2500000>;
				regulator-name = "+V2.5_ETH (PMIC LDO2)";
			};

			reg_vda_dll: ldo3 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <800000>;
				regulator-name = "+V0.8_VDA_DLL (PMIC LDO3)";
			};

			reg_vda_pll: ldo4 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-name = "+V0.8_VDA_PLL (PMIC LDO4)";
			};
		};
	};

	sensor@4f {
		compatible = "ti,tmp1075";
		reg = <0x4f>;
	};

	som_eeprom: eeprom@50 {
		compatible = "st,24c02", "atmel,24c02";
		pagesize = <16>;
		reg = <0x50>;
	};
};

&wkup0_crit {
	temperature = <105000>;
};

&wkup0_thermal {
	trips {
		wkup0_alert0: trip-point0 {
			temperature = <70000>;
			hysteresis = <2000>;
			type = "active";
		};

		wkup0_alert1: trip-point1 {
			temperature = <85000>;
			hysteresis = <2000>;
			type = "active";
		};
	};
};

&wkup1_crit {
	temperature = <105000>;
};

&wkup1_thermal {
	trips {
		wkup1_alert0: trip-point0 {
			temperature = <70000>;
			hysteresis = <2000>;
			type = "active";
		};

		wkup1_alert1: trip-point1 {
			temperature = <85000>;
			hysteresis = <2000>;
			type = "active";
		};
	};
};

&wkup_gpio_intr {
	status = "okay";
};

/* Aquila UART_2 */
&wkup_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wkup_uart0>;
	status = "disabled";
};

0 Gokul Praveen 6 days ago in reply to Ernest Van Hoecke

TI__Genius 14400 points

Hi Ernest,

Ernest Van Hoecke said:
How can I verify these SW2 settings? The port is in OTG/DR mode in the device tree to support the gadget.

Just ensuring that the SW2.3 and SW2.4 is set to 1X(Upstream Facing Port) will ensures that it is in device mode.

Ernest Van Hoecke said:
We also have a doubt about this SerDes configuration. Can we expect different issues (aside from the one discussed here) with our current configuration? We were under the impression that the limit on the SerDes was 2 protocols, not 2 IPs. If that is wrong it is an immediate problem for us and we should find a solution. Any other tests I should run to verify that everything is okay?

Sorry for the wrong wordings. It is actually 2 protocols and not 2 IP'S.

Ernest Van Hoecke said:
- The R5 SPL indeed always comes up, but occasionally fails to create the USB gadget. Specifically to set the pullup on D+.

Can you try applying this patch and share the logs, Ernest.

This won't fix the issue but it will tell us which function is causing the 'disconnect'.

diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
index a30c40ef80e..3b2c5c8e88a 100644
--- a/drivers/usb/cdns3/gadget.c
+++ b/drivers/usb/cdns3/gadget.c
@@ -1336,6 +1336,7 @@ static void cdns3_check_usb_interrupt_proceed(struct cdns3_device *priv_dev,
 
 	/* Disconnection detected */
 	if (usb_ists & (USB_ISTS_DIS2I | USB_ISTS_DISI)) {
+		dev_err(priv_dev->dev, "Disconnection detected\n");
 		cdns3_disconnect_gadget(priv_dev);
 		priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
 		usb_gadget_set_state(&priv_dev->gadget, USB_STATE_NOTATTACHED);
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index 04b85419931..7cd6bb41a0d 100644
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -122,8 +122,10 @@ int usb_function_deactivate(struct usb_function *function)
 	struct usb_composite_dev	*cdev = function->config->cdev;
 	int				status = 0;
 
-	if (cdev->deactivations == 0)
+	if (cdev->deactivations == 0) {
+		printf("%s: Disconnecting\n", __func__);
 		status = usb_gadget_disconnect(cdev->gadget);
+	}
 	if (status == 0)
 		cdev->deactivations++;
 
diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c
index 631969b3405..77d382a6f13 100644
--- a/drivers/usb/gadget/g_dnl.c
+++ b/drivers/usb/gadget/g_dnl.c
@@ -101,7 +101,7 @@ static int g_dnl_unbind(struct usb_composite_dev *cdev)
 {
 	struct usb_gadget *gadget = cdev->gadget;
 
-	debug("%s: calling usb_gadget_disconnect for "
+	printf("%s: calling usb_gadget_disconnect for "
 			"controller '%s'\n", __func__, gadget->name);
 	usb_gadget_disconnect(gadget);
 
diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c
index 6bb419ae2ab..bf412fdc3a6 100644
--- a/drivers/usb/gadget/udc/udc-core.c
+++ b/drivers/usb/gadget/udc/udc-core.c
@@ -223,7 +223,7 @@ EXPORT_SYMBOL_GPL(usb_add_gadget_udc);
 
 static void usb_gadget_remove_driver(struct usb_udc *udc)
 {
-	dev_dbg(&udc->dev, "unregistering UDC driver [%s]\n",
+	dev_err(&udc->dev, "unregistering UDC driver [%s]\n",
 			udc->driver->function);
 
 	usb_gadget_disconnect(udc->gadget);

Regards

Gokul Praveen

0 Ernest Van Hoecke 1 day ago in reply to Gokul Praveen

Prodigy 110 points

Hi Gokul,

Gokul Praveen said:
Just ensuring that the SW2.3 and SW2.4 is set to 1X(Upstream Facing Port) will ensures that it is in device mode.

We don't use a switch on our Aquila development board to select the USB Type C port mode. My understanding is that this should all be handled by the CC lines.

Gokul Praveen said:
Sorry for the wrong wordings. It is actually 2 protocols and not 2 IP'S.

Thanks for confirming this, we have also received the guidance that "PCIe0 + PCIe2 + SGMII might be possible assuming the PCIe0 and PCIe2 use the same CLK. I think the number of reference clocks per SERDES is the limiting factor." in previous e-mails about the SerDes limits. Is our configuration as I linked in the earlier comment correct?

Gokul Praveen said:
Can you try applying this patch and share the logs, Ernest.

This won't fix the issue but it will tell us which function is causing the 'disconnect'.

None of this code is ever executed. The SPL hangs inside `common/dfu.c:run_usb_dnl_gadget`. It stays inside that infinite loop waiting for DFU. But because from the perspective of the host PC, the gadget never came up, nothing happens and it never exits. The pullup on the D+ line is never set, which means the host PC does not know a new USB device joined the bus and will never try to enumerate the device, and nothing happens.

I added this patch but there is no new visible output between a working and failed run.

I can however press CTRL+C to exit the infinite loop to produce the following output:

U-Boot SPL 2024.04-00816-g33f4c48792c0 (Dec 16 2025 - 11:18:56 +0100)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
HW CFG: 0x00
Initialized 4 DRAM controllers
SPL initial stack usage: 13456 bytes
Trying to boot from DFU

[[[ PRESSED CTRL+C, normally the output ends here ]]]

unregistering UDC driver []
g_dnl_unbind: calling usb_gadget_disconnect for controller 'cdns3-gadget'
SPL: failed to boot from all boot devices

Thanks,
Ernest

0 Gokul Praveen 1 day ago in reply to Ernest Van Hoecke

TI__Genius 14400 points

HI Ernest,

Thank you for your prompt reply.

Ernest Van Hoecke said:
We don't use a switch on our Aquila development board to select the USB Type C port mode. My understanding is that this should all be handled by the CC lines.

Regarding this, have you tried stress testing on the J784S4 TI EVM . Ideally the CC lines are controlled by this switch on TI J784S4 EVM.

Ernest Van Hoecke said:
Thanks for confirming this, we have also received the guidance that "PCIe0 + PCIe2 + SGMII might be possible assuming the PCIe0 and PCIe2 use the same CLK. I think the number of reference clocks per SERDES is the limiting factor." in previous e-mails about the SerDes limits. Is our configuration as I linked in the earlier comment correct?

Regarding this, I have looped in the serdes expert to comment on this.

Ernest Van Hoecke said:
None of this code is ever executed. The SPL hangs inside `common/dfu.c:run_usb_dnl_gadget`. It stays inside that infinite loop waiting for DFU. But because from the perspective of the host PC, the gadget never came up, nothing happens and it never exits. The pullup on the D+ line is never set, which means the host PC does not know a new USB device joined the bus and will never try to enumerate the device, and nothing happens.

I added this patch but there is no new visible output between a working and failed run.

I can however press CTRL+C to exit the infinite loop to produce the following output:

Regarding this, I see these 2 prints coming up in your logs , which is present in our patch. I will dig deeper into these messages and get back to you, Ernest.

unregistering UDC driver []
g_dnl_unbind: calling usb_gadget_disconnect for controller 'cdns3-gadget'

Regards

Gokul Praveen

0 Ernest Van Hoecke 23 hours ago in reply to Gokul Praveen

Prodigy 110 points

Hi Gokul,

Thanks for your prompt relies as well.

Gokul Praveen said:
Regarding this, have you tried stress testing on the J784S4 TI EVM . Ideally the CC lines are controlled by this switch on TI J784S4 EVM.

I could consider this if there's a good reason but it would take some work and as it stands to me this seems to be a clear bug somewhere in the USB hardware/configuration since it's so sporadic.

Gokul Praveen said:
Regarding this, I see these 2 prints coming up in your logs , which is present in our patch. I will dig deeper into these messages and get back to you, Ernest.

To me this is just expected behaviour from forcefully exiting that loop. These messages are never seen in the normal failed case if you don't press CTRL+C. Once you exit the loop or finish programming of course it will unregister the UDC driver and stop the gadget, but it tells us nothing about why the initialization of the USB gadget is failing and why the D+ line is never pulled up and the USB IP is not behaving as expected.

Kind regards,
Ernest

0 Siddharth Vadapalli 23 hours ago in reply to Gokul Praveen

TI__Expert 3735 points

Hello Ernest,

Gokul Praveen said:
Ernest Van Hoecke said:
Thanks for confirming this, we have also received the guidance that "PCIe0 + PCIe2 + SGMII might be possible assuming the PCIe0 and PCIe2 use the same CLK. I think the number of reference clocks per SERDES is the limiting factor." in previous e-mails about the SerDes limits. Is our configuration as I linked in the earlier comment correct?

Regarding this, I have looped in the serdes expert to comment on this.

The following node is incorrect unless you also have the driver support for it:

&serdes0 {
	status = "okay";

	/* Aquila PCIE_2 */
	serdes0_pcie1_2l_link: phy@0 {
		reg = <0>;
		#phy-cells = <0>;
		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
		cdns,num-lanes = <2>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
	};

	/* On-module PCIe Wi-Fi */
	serdes0_pcie3_1l_link: phy@2 {
		reg = <2>;
		#phy-cells = <0>;
		resets = <&serdes_wiz0 3>;
		cdns,num-lanes = <1>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
	};

	/* Aquila USB0 SS */
	serdes0_usb0_ss_link: phy@3 {
		reg = <3>;
		#phy-cells = <0>;
		resets = <&serdes_wiz0 4>;
		cdns,num-lanes = <1>;
		cdns,phy-type = <PHY_TYPE_USB3>;
	};
};

Please remove either of the nodes among serdes0_pcie1_2l_link and serdes0_pcie3_1l_link followed by removing the reference to the same in the respective pcie node. The SERDES driver expects two sub-nodes only (corresponding to two distinct protocols). An alternative is to have a single node for both PCIe instances which spans lanes 0 to 2 (both inclusive) and specifies the cdns,phy-type as PCIe.

Also, to configure SERDES at the R5 SPL stage (tiboot3.bin), the following should be added to am69_sk_r5_defconfig:

CONFIG_SPL_PHY=y
CONFIG_SPL_PHY_CADENCE_TORRENT=y
CONFIG_SPL_PHY_J721E_WIZ=y

The above suggestions are orthogonal to the current discussion wherein D+ line isn't pulled up even when USB is operated in USB 2.0 Only mode (SERDES is not used).

Ernest Van Hoecke said:
None of this code is ever executed. The SPL hangs inside `common/dfu.c:run_usb_dnl_gadget`. It stays inside that infinite loop waiting for DFU. But because from the perspective of the host PC, the gadget never came up, nothing happens and it never exits. The pullup on the D+ line is never set, which means the host PC does not know a new USB device joined the bus and will never try to enumerate the device, and nothing happens.

I added this patch but there is no new visible output between a working and failed run.

I can however press CTRL+C to exit the infinite loop to produce the following output:

Thank you for sharing the results. Given that none of the functions which pull-down the D+ line are ever invoked, it seems to be the case that either cdns3_gadget_pullup() is not invoked in the failing case OR it is invoked but setting USB_CONF_DEVEN is not taking effect sporadically. Could you please apply the following diff and share the results of the stress test?

diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
index a30c40ef80e..028e1f33ee0 100644
--- a/drivers/usb/cdns3/gadget.c
+++ b/drivers/usb/cdns3/gadget.c
@@ -2301,10 +2301,13 @@ static int cdns3_gadget_pullup(struct usb_gadget *gadget, int is_on)
 {
        struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);

-       if (is_on)
+       if (is_on) {
                writel(USB_CONF_DEVEN, &priv_dev->regs->usb_conf);
-       else
+               /* Add a barrier to flush the write */
+               dsb();
+       } else {
                writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf);
+       }

        return 0;
 }

Regards,
Siddharth.

0 Ernest Van Hoecke 19 hours ago in reply to Siddharth Vadapalli

Prodigy 110 points

Hi Siddharth,

Thanks for your input re the SerDes, I will have a look and get back to you soon.

Siddharth Vadapalli said:
Thank you for sharing the results. Given that none of the functions which pull-down the D+ line are ever invoked, it seems to be the case that either cdns3_gadget_pullup() is not invoked in the failing case OR it is invoked but setting USB_CONF_DEVEN is not taking effect sporadically. Could you please apply the following diff and share the results of the stress test?

I have verified multiple times during my testing that cdns3_gadget_pullup() is always invoked, also in the failing case. I have even stopped execution there with an infinite loop and attached GDB. In a working case, the write to the register sets the D+ pullup. In the non-working case it does not, and I can see the same by writing to it with GDB. Normally I can toggle the pullup by writing different values to the register. When it failed, I can't. So the problem is certainly what you mention:

Siddharth Vadapalli said:
it is invoked but setting USB_CONF_DEVEN is not taking effect sporadically

I will start a new stress test with only your patch and comparing it to the effect without your patch, and get back to you once it has statistically significant results. Thanks!

Kind regards,
Ernest

0 Ernest Van Hoecke 1 hour ago in reply to Ernest Van Hoecke

Prodigy 110 points

Hi Siddharth,

These are the stress test results:

Good no-barrier  runs: 6212
Good barrier     runs: 6339
Bad  no-barrier  runs: 375
Bad  barrier     runs:    250

As you can see the difference in failure rates between your patch and no patch at all (this is without any other patches, no USB SuperSpeed, an no SerDes/PCIE configuration changse for now) is low.

Kind regards,

Ernest

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AM69: U-Boot SPL USB DFU: cdns3 occasionally fails to pull up D+ in cdns3_gadget_config