Hello,
The device data sheet describes this as "source asynchronous transmit clock" in (G)MII mode (pp 46, 51). In the Technical Reference Manual, it is defined as being synchronous (pp 1093, 1094). Can you clear this up?
Also, figure 8-9 appears misleading in that it shows GMII_GMTCLK as an input to the processor (from the PHY), when it is defined as an output. Should this input be the MTCLK signal instead?
Finally, the terms GMII mode (used in data sheet) and GIG mode (used in Tech Ref Manual) appear to be interchangeable - is this the case?
Thanks in advance.
Peter Clerico