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AM4372: Inquiry about power

Shuhei Goto
Expert 7490 points

Part Number: AM4372

Hi team,

I have questions regarding the AM4372 power pins and power-down sequence.

  1. In the datasheet section [5.12.1.1 Power Supply Slew Rate Requirement], what specifically are the "internal ESD protection devices" mentioned? Are these clamp diodes or similar? If diodes are used, which lines are they connected to?

  2. In the datasheet section [5.12.1.3 Power-Down Sequencing], it states that the potential difference between VDDS/VDDS_CLKOUT and VDDSHVx[x=1-11] must always be less than 2V during power-down. Is it correct to assume that VDDS/VDDS_CLKOUT exceeding VDDSHV[x] during the power-down sequence is not inherently problematic, as long as the 2V differential requirement is met? Please confirm this understanding.

 

Best regards,
Goto

  • +1
    TI__Mastermind 27766 points

    Hi,

    Thanks for reaching out. We do not share information about the internal device architecture. Customers must follow the slew rate requirements documented in the spec.

    Regarding the question about sequencing, the ideal implementation is to have VDDS and VDDS_CLKOUT ramping down after all the VDDSHV supplies are OFF. If this is not possible, then your understanding is correct. In addition to the "<2V" voltage difference, we also recommend maintaining the VDDS and VDDS_CLKOUT voltage ≥1.5V while the other supplies fully ramp down to minimize in-rush currents.

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    TI__Expert 7490 points

    Hi Brenda, 

    Thank you for answer.

    Brenda Diaz said:
    Regarding the question about sequencing, the ideal implementation is to have VDDS and VDDS_CLKOUT ramping down after all the VDDSHV supplies are OFF. If this is not possible, then your understanding is correct. In addition to the "<2V" voltage difference, we also recommend maintaining the VDDS and VDDS_CLKOUT voltage ≥1.5V while the other supplies fully ramp down to minimize in-rush currents.

    There is about 200ms interval between the ramp down of VDDSHV to the ramp down of VDDS/VDDS_CLKOUT.
    Is this interval no problem

    Best regards,
    Goto

  • 0 in reply to Shuhei Goto
    TI__Mastermind 27766 points

    Just to make sure I understand what your are describing in the previous message: is VDDSHV turned-OFF 200ms before VDDS/VDDS_CLKOUT?

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    TI__Expert 7490 points

    Yes, that's right.

    Best regards,
    Goto

  • +1 in reply to Shuhei Goto
    TI__Mastermind 27766 points

    Hi,

    Not sure if I'm understanding the concern here. Turning-OFF VDDS/VDDS_CLKOUT after VDDSHV  is actually that the datasheet recommends. 

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    TI__Expert 7490 points

    Hi

    The concern that "the interval between VDDSHV turnig-off and VDDS/VDDS_CLKOUT is 200ms. Is this not too long?"

    Thank you,
    Goto

  • +1 in reply to Shuhei Goto
    TI__Mastermind 27766 points

    Thanks for clarifying. 200ms is significantly higher than any power-down time slot we have characterized on bench. Our recommendation is to adjust the power-down sequence to have VDDS/VDDS_CLKOUT turning-OFF as soon as the VDDSHV supply discharges below ~300mV. 

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    TI__Expert 7490 points

    Hi Brenda,

    During testing, VDDSHV[x] (configured at 3.3V) clamps at approximately 1.3V until VDDS/VDDS_CLKOUT begins to ramp down.
    Is it possible for an internal current path to form within the CPU from VDDS/VDDS_CLKOUT to VDDSHV[x]?

    Best regards,
    Goto

  • 0 in reply to Shuhei Goto
    TI__Mastermind 27766 points

    Do you see this issue after reducing the 200ms power down timing between VDDSHV and VDDS/VDDS_CLKOUT?

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    TI__Expert 7490 points

    Hi Brenda,

    Even with the reduction from 200ms to 20ms, clamping is still occurring.

    Is it preferable to shut off DDS, VDDS_CLKOUT, and VDDSHV[x] simultaneously?

    Best regards,
    Goto

  • 0 in reply to Shuhei Goto
    TI__Mastermind 27766 points

    Are you using a TI recommended power solution for AM437x or this is a custom power solution? How are you triggering the power-down sequence (removing the pre-regulator or there is a controlled ON/OFF logic)? Could you share the schematic through private E2E and a scope capture for ALL the SoC rails ramping down? When capturing the power-down for each supply group, please use the same oscilloscope trigger so we can analyze the timing between signals. 

    Note: Bandwidth for power related technical support will be limited from Dec-17 until Jan-7. Thanks in advance for your patience.   

    Thanks,

    Brenda