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Stereo audio with evmomapl137

Guillaume Gautier
Prodigy 50 points
Other Parts Discussed in Thread: OMAP-L137

Hello,

I'm using an evmomapl137 board from Spectrum Digital for educational purpose. What I would like to do is to send a signal to the microphone input, filter it with the DSP, and send it back to headphone output, all of this with the interruptions. While I have succeeded in doing that (I see the signal on the oscilloscope), there is no difference between the left and the right channel, despite modifying the balance on the computer.

The board is equiped with an OMAP-L137 and an AIC3106 audio codec. After studying the manual of the McASP of the omap and the codec, I was unable to find the source of my problems. I tried to compare with several configurations I found on the net without success. I don't even know if the problem comes from the McASP or the AIC3106...

Does anyone ever realize a similar thing or have the explanation of this problem?

Thank you in advance

Guillaume

 

Here is the configuration I'm using for the AIC3106:

int16_t

EVMOMAPL137_AIC3106_open (void)

{

// Configure AIC3106

EVMOMAPL137_AIC3106_rset( AIC3106_PAGESELECT, 0 );

// Select page 0

EVMOMAPL137_AIC3106_rset( AIC3106_RESET, 0x80 );

// Reset AIC3106

// Configure AIC3106 registers

EVMOMAPL137_AIC3106_rset( 3, 0x22 );// 5 PLL A <- [PLL=OFF][Q=4][P=2]

EVMOMAPL137_AIC3106_rset( 4, 0x20 );// 4 PLL B <- [J=8]

EVMOMAPL137_AIC3106_rset( 5, 0x6E );// 5 PLL C <- [D=7075]

EVMOMAPL137_AIC3106_rset( 6, 0x23 );// 6 PLL D <- [D=7075]

EVMOMAPL137_AIC3106_rset( 7, 0x0A );// 7 Codec Datapath Setup <- [FS=48 kHz][LeftDAC=LEFT][RightDAC=RIGHT]

EVMOMAPL137_AIC3106_rset( 8, 0x00 );// 8 Audio Interface Control A <- [BCLK=Slave][MCLK=Slave]

EVMOMAPL137_AIC3106_rset( 9, 0x00 );// 9 Audio Interface Control B <- [I2S mode][16 bit]

EVMOMAPL137_AIC3106_rset( 10, 0x00);// 10 Audio Interface Control C <- [Data offset=0]

EVMOMAPL137_AIC3106_rset( 15, 0x17 );// 15 Left ADC PGA Gain <- [Mute=OFF][Gain=8.5dB]

EVMOMAPL137_AIC3106_rset( 16, 0x17 );// 16 Right ADC PGA Gain <- [Mute=OFF][Gain=8.5dB]

EVMOMAPL137_AIC3106_rset( 17, 0x0F );// 17 MIC3L/R to Left ADC <- [MIC3L=0dBGain][MIC3R=NotConnect]

EVMOMAPL137_AIC3106_rset( 18, 0xF0 );// 18 MIC3L/R to Right ADC <- [MIC3L=NotConnect][MIC3R=0dBGain]

EVMOMAPL137_AIC3106_rset( 19, 0x7C );// 19 LINE1L to Left ADC <- [SingleEnd][NotConnect][Power=ON][SoftStep=OncePerFS]

EVMOMAPL137_AIC3106_rset( 22, 0x7C );// 22 LINE1R to Right ADC <- [SingleEnd][NotConnect][Power=ON][SoftStep=OncePerFS]

EVMOMAPL137_AIC3106_rset( 25, 0x40 );// 25 MICBIAS <- [MICBIAS=2.0V]

EVMOMAPL137_AIC3106_rset( 27, 0 );// 27 Left AGC B <- [OFF]

EVMOMAPL137_AIC3106_rset( 30, 0 );// 30 Right AGC B <- [OFF]

EVMOMAPL137_AIC3106_rset( 37, 0xE0 ); // 37 DAC Power & Output Dvr <- [LeftDAC=ON][RightDAC=ON][HPLCOM=SingleEnd]

EVMOMAPL137_AIC3106_rset( 38, 0x10 ); // 38 High Power Output Dvr <- [HPRCOM=SingleEnd][ShortCircuit=OFF]

EVMOMAPL137_AIC3106_rset( 43, 0 );// 43 Left DAC Digital Volume <- [Mute=OFF][Gain=0dB]

EVMOMAPL137_AIC3106_rset( 44, 0 );// 44 Right DAC Digital Volume <- [Mute=OFF][Gain=0dB]

EVMOMAPL137_AIC3106_rset( 47, 0x80 );// 47 DAC_L1 to HPLOUT Volume <- [Routed]

EVMOMAPL137_AIC3106_rset( 51, 0x09 );// 51 HPLOUT Output <- [Mute=OFF][Power=ON]

EVMOMAPL137_AIC3106_rset( 58, 0 );// 58 HPLCOM Output <- []

EVMOMAPL137_AIC3106_rset( 64, 0x80 );// 64 DAC_R1 to HPROUT Volume <- [Routed]

EVMOMAPL137_AIC3106_rset( 65, 0x09 );// 65 HPROUT Output <- [Mute=OFF][Power=ON]

EVMOMAPL137_AIC3106_rset( 72, 0 );// 72 HPRCOM Output <- []

EVMOMAPL137_AIC3106_rset( 82, 0x80 );// 82 DAC_L1 to LEFT_LOP/M Volume <- [Routed]

EVMOMAPL137_AIC3106_rset( 86, 0x09 );// 86 LEFT_LOP/M Output <- [Mute=OFF][Power=ON]

EVMOMAPL137_AIC3106_rset( 92, 0x80 );// 92 DAC_R1 to RIGHT_LOP/M Volume <- [Routed]

EVMOMAPL137_AIC3106_rset( 93, 0x09 );// 93 RIGHT_LOP/M Output <- [Mute=OFF][Power=ON]

EVMOMAPL137_AIC3106_rset( 101, 0x01 );// 101 GPIO Control Register B <- [CODEC_CLKIN = CLKDIV_OUT]

EVMOMAPL137_AIC3106_rset( 102, 0 );// 102 Clock Generation Control <- [PLLCLK_IN and CLKDIV_IN use MCLK]

return 0;

}

 

And the configuration of the McASP:

int16_t

EVMOMAPL137_MCASP_open (void)

{

mcasp = &MCASP_MODULE_1;

mcasp->regs->GBLCTL = 0; // Reset

mcasp->regs->RGBLCTL = 0; // Reset RX

mcasp->regs->XGBLCTL = 0; // Reset TX

mcasp->regs->PWRDEMU = 1; // Free-running

// RX

mcasp->regs->RMASK = 0xffffffff; // No padding used

mcasp->regs->RFMT = 0x00008078; // MSB 16bit, 1-delay, no pad, CFGBus

mcasp->regs->AFSRCTL = 0x00000112; // 2TDM, 1bit Rising, INTERNAL FS, word

mcasp->regs->ACLKRCTL = 0x000000AF; // Rising INTERNAL CLK,(from tx side)

mcasp->regs->AHCLKRCTL = 0x00000000; // INT CLK (from tx side)

mcasp->regs->RTDM = 0x00000003; // Slots 0,1

mcasp->regs->RINTCTL = 0x00000000; // Not used

mcasp->regs->RCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256

// TX

mcasp->regs->XMASK = 0xffffffff; // No padding used

mcasp->regs->XFMT = 0x00008078; // MSB 16bit, 1-delay, no pad, CFGBus

mcasp->regs->AFSXCTL = 0x00000112; // 2TDM, 1bit Rising edge INTERNAL FS, word

mcasp->regs->ACLKXCTL = 0x000000AF; // ASYNC, Rising INTERNAL CLK, div-by-16

mcasp->regs->AHCLKXCTL = 0x00000000; // EXT CLK

mcasp->regs->XTDM = 0x00000003; // Slots 0,1

mcasp->regs->XINTCTL = 0x00000000; // Not used

mcasp->regs->XCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256

mcasp->regs->SRCTL5 = 0x000D; // MCASP1.AXR1[5] --> DIN

mcasp->regs->SRCTL0 = 0x000E; // MCASP1.AXR1[0] <-- DOUT

mcasp->regs->PFUNC = 0; // All MCASPs

mcasp->regs->PDIR = 0x14000020; // All inputs except AXR0[5], ACLKX1, AFSX1

mcasp->regs->DITCTL = 0x00000000; // Not used

mcasp->regs->DLBCTL = 0x00000000; // Not used

mcasp->regs->AMUTE = 0x00000000; // Not used

// Starting sections of the McASP

mcasp->regs->XGBLCTL |= GBLCTL_XHCLKRST_ON; // HS Clk

while ( ( mcasp->regs->XGBLCTL & GBLCTL_XHCLKRST_ON ) != GBLCTL_XHCLKRST_ON );

mcasp->regs->RGBLCTL |= GBLCTL_RHCLKRST_ON; // HS Clk

while ( ( mcasp->regs->RGBLCTL & GBLCTL_RHCLKRST_ON ) != GBLCTL_RHCLKRST_ON );

mcasp->regs->XGBLCTL |= GBLCTL_XCLKRST_ON; // Clk

while ( ( mcasp->regs->XGBLCTL & GBLCTL_XCLKRST_ON ) != GBLCTL_XCLKRST_ON );

mcasp->regs->RGBLCTL |= GBLCTL_RCLKRST_ON; // Clk

while ( ( mcasp->regs->RGBLCTL & GBLCTL_RCLKRST_ON ) != GBLCTL_RCLKRST_ON );

mcasp->regs->XSTAT = 0x0000ffff; // Clear all

mcasp->regs->RSTAT = 0x0000ffff; // Clear all

mcasp->regs->XGBLCTL |= GBLCTL_XSRCLR_ON; // Serialize

while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSRCLR_ON ) != GBLCTL_XSRCLR_ON );

mcasp->regs->RGBLCTL |= GBLCTL_RSRCLR_ON; // Serialize

while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSRCLR_ON ) != GBLCTL_RSRCLR_ON );

// Write a 0, so that no underrun occurs after releasing the state machine

mcasp->regs->XBUF5= 0;

mcasp->regs->XGBLCTL |= GBLCTL_XSMRST_ON; // State Machine

while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSMRST_ON ) != GBLCTL_XSMRST_ON );

mcasp->regs->RGBLCTL |= GBLCTL_RSMRST_ON; // State Machine

while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSMRST_ON ) != GBLCTL_RSMRST_ON );

mcasp->regs->XGBLCTL |= GBLCTL_XFRST_ON; // Frame Sync

while ( ( mcasp->regs->XGBLCTL & GBLCTL_XFRST_ON ) != GBLCTL_XFRST_ON );

mcasp->regs->RGBLCTL |= GBLCTL_RFRST_ON; // Frame Sync

while ( ( mcasp->regs->RGBLCTL & GBLCTL_RFRST_ON ) != GBLCTL_RFRST_ON );

// Start by sending a dummy write

while( ! ( mcasp->regs->SRCTL5 & 0x10 ) ); // Check for Tx ready

mcasp->regs->XBUF5 = 0;

return 0;

}

  • 0
    TI__Expert 8890 points

    Guillaume,

    Does the data appear different during the processing phase of your application?  You may also want to try something drastic (i.e. zero out the left channel) to see if you can force any difference between the channels.

    Also, what did you use as the starting point for your application development?  If you haven't seen this already, I recommend taking a look at the low-level audio application for C6747 that demonstrates using EDMA to collect incoming data into left and right buffers for easier, more efficient processing:

    Hope this helps.

  • 0 in reply to Joe Coombs
    Prodigy 50 points

    Joe,

    Thanks for your reply. I had already tried to put zero on one channel but all I obtained on the oscilloscope was a kind of "mean": the two channels were always identical (weaker, but identical). The link you gave me allows me to differentiate the channels but it uses the EDMA, which I don't really want to use, at least at first. Now I'll try to determine what causes my problem by comparing this version with mine, and hopefully correct it.

    Guillaume