PCIe Burst Transfers using QDMA

Hakan,

The QDMA is similar as DMA that could be used for data transfer between most of the peripherals including the PCIe. The major difference between QDMA and DMA is the event/channel synchronization. QDMA events are either auto-triggered or link triggered, while DMA could be manually triggered as well. Please refer to section 2.4.3 in EDMA user's guide for details to see if QDMA suits your need.

If you prefer the PCIe TLP payload size to be 128 bytes, you may also need to choose the QDMA/DMA queues which support DBS=128 bytes, because some of the transfer queues only support 64-byte DBS. That means even you program the ACNT in QDMA/DMA to be 128B (pcie_max_payload in your example code), the QDMA/DMA will still generate the 64B as the data payload in each PCIe packet. Please refer to the device data manual for the details. For example, table 7-34 in C6678 data manual has the details of the  EDMA3 configurations.

Please also note that the QDMA example code in the CSL you mentioned does not use the API to modify the transfer queue to be used. By default, the transfer queue 0 (TC0) will be used. It should be working for C6678 since the TC0 has DBS=128B for all the EDMA3 channel controllers (selected by "instNum" in example code). If you would like to change the transfer queue, you may need to use "CSL_edma3HwChannelSetupQue()" or "CSL_edma3MapQDMAChannelToEventQueue()" described in the CSL document.

Sincerely,

Steven

Hello Steven,

Thanks for your reply. I will try QDMA for my PCIe transfers with 128-bytes of TLP. However, I am confused with whether there is an association required between the EDMA3
channel controller (which is 0 for me) and PCIESS?

If the answer is yes, how can I do it?

Regards,
Hakan

Hakan,

You can use ANY QDMA/DMA channel controller and transfer controller to access the PCIe slave port in C667x devices. Please refer to System Interconnect section in the device data manual. You can regard PCIe data space (starting from 0x60000000) as a memory endpoint for the QDMA/DMA. There is no association required between them.

You can choose to use some specific QDMA/DMA transfer controller (with DBS=128B) to improve the performance of PCIe throughput but it is not a requirement.

Sincerely,

Steven

Hi,

Steven Ji said:

You can regard PCIe data space (starting from 0x60000000) as a memory endpoint for the QDMA/DMA

Does this mean that the pcieBase pointer (along with the Pcie_getMemSpaceRange function) can be used as the destination buffer (dstBuf) for a DMA transfer to place data in the PCIe data space such that an end point can access it?

Would a similar access by the end point, using pcieBase as the source buffer (src buf), be able to copy this data out of the PCIe data space and into DDR?

Thx

Charles

Charles,

The PCIe data space is the memory region space defined in the memory map of the device to access the PCIe data.

You can use the pcieBase from Pcie_geMemSpaceRange as an dstBuff for DMA. The DMA will transfer data from source buffers to the PCIe data space (dstBuff) and data will be translated into PCIe packets with PCIe address and be transmitted over the PCIe link to the external device.

You can also use pcieBase as the srcBuff for DMA. The DMA will fetch the data from the PCIe data space (data from external device being transferred over the PCIe link) and put them into the internal memory location defined dstBuff of DMA.