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AM625: tDQSS

Steve Schefter
Prodigy 70 points

Part Number: AM625
Other Parts Discussed in Thread: AM623, SYSCONFIG

Hi.  We are using the TI AM623/AM625 DDR Subsystem Sysconfig to generate the DRAM configuration for timing (k3-am62x-ddr-config.dtsi for u-boot SPL/tiboot3.bin).

We observe that the DQS signals are delayed from the DDR clock edge (see trace below).

In DRAM datasheets, this is tDQSS.  However, I'm not seeing such a parameter in sysconfig variables.  The closest is tDQSCKmax, but unforunately the meaning of that variable isn't clear and adjusting it has no impact on the DQS delay.

How can we control when the processor drives DQSS relative to the DDR clock during a write cycle?

Thanks,
    Steve


CLKvsDQS.jpg

  • +1
    TI__Guru* 96101 points

    Hi Steve, this is not something specifically to set in the sysconfig tool.  The DQS and CK signals are adjusted during initialization and training (specifically write leveling).  If they are not aligned, this may indicate something is not quite right with the training procedure.  Also, the spec for tDQSS is at the memory pins, so if you are probing elsewhere on the trace, you may observe some skew between the signals.  

    Based on your scope shot, i think i see about 0.3ns of skew?  I agree they could be better aligned, but i think this is within spec.  Are you using LPDDR4 or DDR4?

    Do you have the DDR datasheet (or part number) and the .syscfg file from the tool?  i can help double check your configuration

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 70 points

    Thank you very much James.

    It's a MT40A1G16TB-062E IT:F.  Below is the current syscfg file.  It has tDQSCKmax_ns set to 0 as commented on above, though it should really be .160ns.

    Regards,
        Steve

    /**
     * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
     * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
     * @cliArgs --device "AM62x" --part "Default" --package "ALW" --product "Processor_DDR_Config@0.10.32"
     * @v2CliArgs --device "AM625" --package "FCBGA (ALW)" --variant "AM6254-G" --product "Processor_DDR_Config@0.10.32"
     * @versions {"tool":"1.25.0+4268"}
     */

    /**
     * Import the modules used in this configuration.
     */
    const DDRSS = scripting.addModule("/DDRSS");

    /**
     * Write custom configuration values to the imported modules.
     */
    DDRSS.ddr4.$name                         = "sitara_ddr4_DDRSS_DDR40";
    DDRSS.ddr4.config_dram_mr0_cl            = 22;
    DDRSS.ddr4.system_cfg_dram_density       = 8;
    DDRSS.ddr4.config_dram_tFAW_tCK          = 16;
    DDRSS.ddr4.config_dram_tXPR_tCK          = 288;
    DDRSS.ddr4.config_dram_tWR_CRC_DM_ns     = 18.75;
    DDRSS.ddr4.config_dram_mr5_ca_par_lat    = "4 clocks";
    DDRSS.ddr4.config_dram_tCCD_L_ns         = 6.25;
    DDRSS.ddr4.config_dram_tFAW_ns           = 20;
    DDRSS.ddr4.config_dram_tPAR_ALERT_PW_tCK = 43;
    DDRSS.ddr4.config_dram_tRASmin_ns        = 32;
    DDRSS.ddr4.config_dram_tRRD_L_ns         = 7.5;
    DDRSS.ddr4.config_dram_tRRD_S_ns         = 6;
    DDRSS.ddr4.config_dram_tWR_CRC_DM_tCK    = 19;
    DDRSS.ddr4.config_dram_tDQSCKmax_ns      = 0;

  • 0 in reply to Steve Schefter
    TI__Guru**** 233815 points

    Hello Steve,

    Please expect a delayed response due to thanksgiving holidays.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru* 96101 points

    Hi Steve, based on the datasheet you sent, you should just be able to use the default configuration file: 

     /cfs-file/__key/communityserver-discussions-components-files/791/k3_2D00_am64_2D00_ddr_2D00_config-_2800_4_2900_.dtsi

    The changes you made do not line up with the values in the datasheet.  For example. the tFAW values you set do not represent a 2KB page device at -062 speed grade (DDR4-3200).

     

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 70 points

    Thanks James.  My preference is to have a defined set of input to sysconfig rather than relying on generated dtsi file.  That way, should we change to a different DRAM chip with slightly different timing, we can tweak the parameters.  Tweaking the generated file would be a challenge.  Interestingly, correcting tFAW made no difference to the generated k3-am62x-ddr-config.dtsi.

    Regards,
        Steve

  • 0 in reply to Steve Schefter
    TI__Guru* 96101 points

    Hi Steve, did you revert the other changes you made?  I was just showing tFAW as one example.  You can see the defined set of inputs for the default config in the settings_info.syscfg file

    Regards,

    James